Patents by Inventor Prashant Choudhary

Prashant Choudhary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10568336
    Abstract: A yogurt maker device comprises an outer shell to house a yogurt vessel that receives milk and a culture container that receives yogurt culture. A processor within the outer shell controls a heating element to boil milk within the yogurt vessel using a temperature sensor as feedback and for maintaining a predefined boiling temperature for a predefined period of boiling time and a stirring device to continuously stir boiling milk within the yogurt vessel while boiling and also while cooling to a cooling predefined temperature until fermentation temperature is reached. The processor also controls a culture container base holding the culture container and having a motor to automatically pour the yogurt culture when the fermentation temperature is reached. Finally, a cooling mechanism automatically provides cooling to contents of the yogurt vessel once fermentation is complete.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: February 25, 2020
    Assignee: JOGURT, LLC
    Inventors: Prashant Choudhary, Suresh Chandrasekaran
  • Patent number: 10555633
    Abstract: An automatic cooking device creates a recipe file based on an actual cooking session by an individual. The same dish can be automatically recreated on demand from the recipe file, wherein an optimal remaining cooking time is automatically determined responsive to an image analysis of real-time image sensor feedback versus reference image. In some implementations, recipe files are acquired through a network and downloaded for a fee.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: February 11, 2020
    Inventor: Prashant Choudhary
  • Patent number: 10320370
    Abstract: Methods and circuits for analyzing a signal and adjusting parameters of an equalizer for a signal. The signal is received at a receiver over a channel wherein the signal has a wave form. The signal is equalized at an equalizer using an adjustable parameter for the equalization. Data points from the signal are sampled between upper and lower limits of a threshold at an error sampler. A performance metric of the signal is computed based on a statistical density of the data points from the signal between the upper and lower limits of the threshold.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: June 11, 2019
    Assignee: MoSys, Inc.
    Inventors: Prashant Choudhary, Haidang Lin, Alvin Wang, Saman Behtash, Shaishav Desai
  • Publication number: 20170156358
    Abstract: A yogurt maker device comprises an outer shell to house a yogurt vessel that receives milk and a culture container that receives yogurt culture. A processor within the outer shell controls a heating element to boil milk within the yogurt vessel using a temperature sensor as feedback and for maintaining a predefined boiling temperature for a predefined period of boiling time and a stirring device to continuously stir boiling milk within the yogurt vessel while boiling and also while cooling to a cooling predefined temperature until fermentation temperature is reached. The processor also controls a culture container base holding the culture container and having a motor to automatically pour the yogurt culture when the fermentation temperature is reached. Finally, a cooling mechanism automatically provides cooling to contents of the yogurt vessel once fermentation is complete.
    Type: Application
    Filed: December 2, 2016
    Publication date: June 8, 2017
    Inventors: Prashant CHOUDHARY, SURESH CHANDRASEKARAN
  • Publication number: 20160278563
    Abstract: An automatic cooking device creates a recipe file based on an actual cooking session by an individual. The same dish can be automatically recreated on demand from the recipe file, wherein an optimal remaining cooking time is automatically determined responsive to an image analysis of real-time image sensor feedback versus reference image. In some implementations, recipe files are acquired through a network and downloaded for a fee.
    Type: Application
    Filed: March 28, 2016
    Publication date: September 29, 2016
    Inventor: Prashant CHOUDHARY
  • Patent number: 9148154
    Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: September 29, 2015
    Assignee: MoSys, Inc.
    Inventors: Prashant Choudhary, Aldo Bottelli, Charles W Boecker
  • Publication number: 20150263737
    Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
    Type: Application
    Filed: March 31, 2014
    Publication date: September 17, 2015
    Applicant: MOSYS, INC.
    Inventors: Prashant Choudhary, Aldo Bottelli, Charles W. Boecker
  • Publication number: 20150244381
    Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
    Type: Application
    Filed: March 31, 2014
    Publication date: August 27, 2015
    Applicant: MoSys, Inc.
    Inventors: Prashant Choudhary, Aldo Bottelli, Charles W. Boecker
  • Publication number: 20140218083
    Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
    Type: Application
    Filed: March 31, 2014
    Publication date: August 7, 2014
    Applicant: MoSys, Inc.
    Inventors: Prashant Choudhary, Aldo Bottelli, Charles W. Boecker
  • Publication number: 20140210531
    Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
    Type: Application
    Filed: March 31, 2014
    Publication date: July 31, 2014
    Applicant: MOSYS, INC.
    Inventors: Prashant Choudhary, Aldo Bottelli, Charles W. Boecker
  • Patent number: 8704570
    Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: April 22, 2014
    Assignee: MoSys, Inc.
    Inventors: Aldo Bottelli, Prashant Choudhary, Charles W Boecker
  • Publication number: 20130154698
    Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 20, 2013
    Applicant: MoSys, Inc
    Inventors: Aldo Bottelli, Prashant Choudhary, Charles W. Boecker
  • Patent number: 8136081
    Abstract: A performance optimizing circuit is provided for a signal processing system which is parameterized by a set of coefficients that vary the operational characteristics of the signal processing system. The performance optimizing circuit receives as input a reference signal and an output signal of the signal processing system. The performance optimizing circuit may include (a) a cost computation circuit that receives the reference signal and the output signal and provides as output a cost signal representing a cost function computed using a set of current values for the set of coefficients, the output signal and the reference signal; and (b) a cost optimizer circuit that, at each of a plurality of successive time intervals, evaluates one or more values of the cost signal in the cost computation circuit and provides to the signal processing system a new set of values for the set of coefficients.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: March 13, 2012
    Assignee: Scintera Networks, Inc.
    Inventors: Arvind V. Keerthi, Prashant Choudhary
  • Publication number: 20110258591
    Abstract: A performance optimizing circuit is provided for a signal processing system which is parameterized by a set of coefficients that vary the operational characteristics of the signal processing system. The performance optimizing circuit receives as input a reference signal and an output signal of the signal processing system. The performance optimizing circuit may include (a) a cost computation circuit that receives the reference signal and the output signal and provides as output a cost signal representing a cost function computed using a set of current values for the set of coefficients, the output signal and the reference signal; and (b) a cost optimizer circuit that, at each of a plurality of successive time intervals, evaluates one or more values of the cost signal in the cost computation circuit and provides to the signal processing system a new set of values for the set of coefficients.
    Type: Application
    Filed: April 16, 2010
    Publication date: October 20, 2011
    Inventors: Arvind V. Keerthi, Prashant Choudhary
  • Patent number: 7561617
    Abstract: Systems and methods are disclosed to provide channel monitoring and/or performance monitoring for a communication channel. For example, in accordance with an embodiment of the present invention, an equalizer is disclosed that equalizes for channel distortions and also provides channel and performance monitoring information, such as for example bandwidth estimation, channel identification, signal-to-noise ratio, chromatic dispersion, and/or polarization-mode dispersion.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: July 14, 2009
    Assignee: INPHI Corporation
    Inventors: Abhijit G. Shanbhag, Abhijit Phanse, Jishnu Bhattacharjee, Debanjan Mukherjee, Prashant Choudhary, Edem Ibragimov, Venugopal Balasubramonian, Qian Yu, Madabusi Govindarajan
  • Patent number: 7505515
    Abstract: A continuous time equalizer for equalizing an input signal using a feedforward equalizer portion and a feedback equalizer portion is provided that includes: a slicer operable to make bit decisions on a combined output from the feedforward and feedback equalizer portions; an adaptive delay circuit operable to delay the combined output to form a delayed output; and a controller operable to control the delay provided by the adaptive delay circuit such that a first group delay through the slicer and a second group delay through the adaptive delay circuit in response to a sinusoidal form of the input signal are substantially equal.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: March 17, 2009
    Assignee: Scintera Networks, Inc.
    Inventors: Prashant Choudhary, Qian Yu, Edem Ibragimov, Venu Balasubramonian, Debanjan Mukherjee, Jishnu Bhattacharjee, Fabian Giroud
  • Patent number: 7421022
    Abstract: A continuous time electronic dispersion compensation architecture using feed forward equalization and a non-linear decision feedback equalization forms an output signal by a linear combination of successively delayed versions of the input signal and the sliced output signal weighted by appropriate coefficients. A selected number of taps in the mixer used to generate a corresponding number of coefficients for use in the feed forward equalizer are held to a selected voltage to ensure that the coefficients associated with these two taps do not drift. This causes the other coefficients to converge to a unique minimum square error value. In one embodiment the selected voltage is the maximum system voltage.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: September 2, 2008
    Assignee: Inphi Corporation
    Inventors: Prashant Choudhary, Venugopal Balasubramonian, Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse, Abhijit Shanbhag, Qian Yu
  • Patent number: 7394849
    Abstract: A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer. The dynamic timing is controlled by a signal formed as a combination of feedback and feedforward signals. The feedback signal is an error signal related to a difference between pre-slicer and post-slicer signals. The feedforward signal is formed by differentiating and delaying the incoming data signal.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: July 1, 2008
    Assignee: Scintera Networks Inc.
    Inventors: Edem Ibragimov, Qian Yu, Prashant Choudhary
  • Patent number: 7339988
    Abstract: Systems and methods are disclosed to provide channel monitoring and/or performance monitoring for a communication channel. For example, in accordance with an embodiment of the present invention, an equalizer is disclosed that equalizes for channel distortions and also provides channel and performance monitoring information, such as for example bandwidth estimation, channel identification, signal-to-noise ratio, chromatic dispersion, and/or polarization-mode dispersion.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: March 4, 2008
    Assignee: Scintera Networks, Inc.
    Inventors: Abhijit G. Shanbhag, Abhijit Phanse, Jishnu Bhattacharjee, Debanjan Mukherjee, Prashant Choudhary, Edem Ibragimov, Venugopal Balasubramonian, Qian Yu, Madabusi Govindarajan
  • Publication number: 20070091995
    Abstract: A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer. The dynamic timing is controlled by a signal formed as a combination of feedback and feedforward signals. The feedback signal is an error signal related to a difference between pre-slicer and post-slicer signals. The feedforward signal is formed by differentiating and delaying the incoming data signal.
    Type: Application
    Filed: October 9, 2006
    Publication date: April 26, 2007
    Applicant: SCINTERA NETWORKS, INC.
    Inventors: Edem Ibragimov, Qian Yu, Prashant Choudhary