Patents by Inventor Prashant Dinkar Karandikar

Prashant Dinkar Karandikar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220189068
    Abstract: Embodiments include methods for image compression and decompression. A sending computing device may determine a type of packing used for a chunk of image data, generate metadata describing the type of packing used for the chunk of image data, pack the chunk of image data according to the determined type of packing, and send the packed chunk of image data and the metadata to a second computing device. A receiving computing device may decode the metadata describing the type of packing used for the chunk of image data, determine the type of packing used for the chunk of image data based on the decoded metadata, and unpack the chunk of image data according to the determined type of packing used for the chunk of image data.
    Type: Application
    Filed: December 11, 2020
    Publication date: June 16, 2022
    Inventors: Andrew Edmund TURNER, Prashant Dinkar KARANDIKAR
  • Publication number: 20200363210
    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Rahul Gulati, Aishwarya Dubey, Nainala Vyagrheswarudu, Vasant Easwaran, Prashant Dinkar Karandikar, Mihir Mody
  • Patent number: 10767998
    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rahul Gulati, Aishwarya Dubey, Nainala Vyagrheswarudu, Vasant Easwaran, Prashant Dinkar Karandikar, Mihir Mody
  • Publication number: 20180364051
    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.
    Type: Application
    Filed: August 28, 2018
    Publication date: December 20, 2018
    Inventors: Rahul Gulati, Aishwarya Dubey, Nainala Vyagrheswarudu, Vasant Easwaran, Prashant Dinkar Karandikar, Mihir Moody
  • Patent number: 10089172
    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: October 2, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rahul Gulati, Aishwarya Dubey, Nainala Vyagrheswarudu, Vasant Easwaran, Prashant Dinkar Karandikar, Mihir Mody
  • Patent number: 9628787
    Abstract: A method for testing an imaging subsystem of a system-on-a-chip (SOC) is provided that includes executing imaging subsystem test software instructions periodically on a processor of the SOC, receiving reference image data in the imaging subsystem responsive to the executing of the test software instructions, performing image signal processing on the reference image data by the imaging subsystem to generate processed reference image data, and using the processed reference image data by the test software instructions to verify whether or not the imaging subsystem is operating correctly.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: April 18, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rahul Gulati, Vasant Easwaran, Mihir Narendra Mody, Prashant Dinkar Karandikar, Prithvi Y. A. Shankar, Aishwarya Dubey, Kedar Chitnis, Rajat Sagar
  • Patent number: 9430393
    Abstract: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: August 30, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prashant Dinkar Karandikar, Mihir Mody, Hetul Sanghavi, Vasant Easwaran, Prithvi Y. A. Shankar, Rahul Gulati, Niraj Nandan, Subrangshu Das
  • Publication number: 20150339234
    Abstract: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.
    Type: Application
    Filed: December 24, 2014
    Publication date: November 26, 2015
    Inventors: Prashant Dinkar Karandikar, Mihir Mody, Hetul Sanghavi, Vasant Easwaran, Prithvi Y.A. Shankar, Rahul Gulati, Niraj Nandan, Subrangshu Das
  • Publication number: 20150304648
    Abstract: A method for testing an imaging subsystem of a system-on-a-chip (SOC) is provided that includes executing imaging subsystem test software instructions periodically on a processor of the SOC, receiving reference image data in the imaging subsystem responsive to the executing of the test software instructions, performing image signal processing on the reference image data by the imaging subsystem to generate processed reference image data, and using the processed reference image data by the test software instructions to verify whether or not the imaging subsystem is operating correctly.
    Type: Application
    Filed: January 27, 2015
    Publication date: October 22, 2015
    Inventors: Rahul Gulati, Vasant Easwaran, Mihir Narendra Mody, Prashant Dinkar Karandikar, Prithvi Y.A. Shankar, Aishwarya Dubey, Kedar Chitnis, Rajat Sagar
  • Publication number: 20150227421
    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.
    Type: Application
    Filed: December 31, 2014
    Publication date: August 13, 2015
    Inventors: Rahul Gulati, Aishwarya Dubey, Nainala Vyagrheswarudu, Vasant Easwaran, Prashant Dinkar Karandikar, Mihir Moody