Patents by Inventor Prashant Goteti

Prashant Goteti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10929337
    Abstract: Methods, systems and apparatuses may provide for technology that detects, by a first monitor in a first domain of a system, a presence of a first anomaly in the first domain and encodes, by the first monitor, the presence of the first anomaly and a weight of the first anomaly into a multi-level data structure. In one example, the technology also sends, by the first monitor, the multi-level data structure to a second monitor in a second domain of the system, wherein the second domain is located at a different hierarchical level in the system than the first domain.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Rahul Kundu, Fei Su, Prashant Goteti
  • Patent number: 10685159
    Abstract: In some examples, systems and methods may be used to improve functional safety of analog or mixed-signal circuits, and, more specifically, to anomaly detection to help predict failures for mitigating catastrophic results of circuit failures. An example may include using a machine learning model trained to identify point anomalies, contextual or conditional anomalies, or collective anomalies in a set of time-series data collected from in-field detectors of the circuit. The machine learning models may be trained with data that has only normal data or has some anomalous data included in the data set. In an example, the data may include functional or design-for-feature (DFx) signal data received from an in-field detector on an analog component. A functional safety action may be triggered based on analysis of the functional or DFx signal data.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Fei Su, Prashant Goteti
  • Publication number: 20190361839
    Abstract: Methods, systems and apparatuses may provide for technology that detects, by a first monitor in a first domain of a system, a presence of a first anomaly in the first domain and encodes, by the first monitor, the presence of the first anomaly and a weight of the first anomaly into a multi-level data structure. In one example, the technology also sends, by the first monitor, the multi-level data structure to a second monitor in a second domain of the system, wherein the second domain is located at a different hierarchical level in the system than the first domain.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 28, 2019
    Inventors: Rahul Kundu, Fei Su, Prashant Goteti
  • Publication number: 20190050515
    Abstract: In some examples, systems and methods may be used to improve functional safety of analog or mixed-signal circuits, and, more specifically, to anomaly detection to help predict failures for mitigating catastrophic results of circuit failures. An example may include using a machine learning model trained to identify point anomalies, contextual or conditional anomalies, or collective anomalies in a set of time-series data collected from in-field detectors of the circuit. The machine learning models may be trained with data that has only normal data or has some anomalous data included in the data set. In an example, the data may include functional or design-for-feature (DFx) signal data received from an in-field detector on an analog component. A functional safety action may be triggered based on analysis of the functional or DFx signal data.
    Type: Application
    Filed: June 27, 2018
    Publication date: February 14, 2019
    Inventors: Fei Su, Prashant Goteti
  • Publication number: 20060005091
    Abstract: In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Subhasish Mitra, Kee Kim, Tak Mak, Prashant Goteti