Patents by Inventor Prashant Karhade

Prashant Karhade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7181383
    Abstract: A system for simulating a circuit having hierarchical data structure includes a simulator module having one or more computer programs for 1) creating a static database in accordance with a netlist description of the circuit, where the static database contains topology information of the circuit; 2) selecting a group circuit for simulation, where the group circuit contains one or more leaf circuits selected from the first branch and the second branch; 3) creating a dynamic database for representing the group circuit, where the dynamic database includes references to the static database for fetching topology information dynamically during simulation; and 4) simulating the group circuit in accordance with the dynamic database. Since the system duplicates and reproduces only the relevant dynamic information when necessary, the disclosed circuit simulator uses less memory and produces better performance.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: February 20, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bruce W. McGaughy, Prashant Karhade, Jaideep Muhkerjee, Jun Kong
  • Patent number: 7143021
    Abstract: A machine-implemented, simulations-supporting system creates a hierarchy of data structures for simplifying the task of identifying iso-topological, and iso-geometric, and iso-static instances of subcircuit-definitions. The behaviors of such isomorphic and iso-static instances can be simultaneously predicted by appointing a simulation leader for them and using the simulation leader in combination with a respective simulation model to predict the behavior of the simulation leader. The predicted behavior of the leader is then copied for the followers. In one embodiment, state-describing S-circuit cards each point to a respective, and possibly merged, I-circuit card. The I-circuit cards each point to respective, and possibly merged, element instantiating cards (AG-cards) as well as to respective, and possibly merged, interconnect-topology describing cards (T-circuits).
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: November 28, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bruce W. McGaughy, Prashant Karhade, Peng Wan, Manish Singh