Patents by Inventor Prashant Malladi

Prashant Malladi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260186951
    Abstract: Model level debugging of a machine learning design includes compiling the machine learning design for execution on target hardware using a compiler. Metadata for the machine is generated. The metadata specifies a mapping of buffers of the machine learning design to a plurality of memory levels of a memory architecture of the target hardware correlated with boundaries of the machine learning design. While running the machine learning design, debug data is dumped from the plurality of memory levels of the memory architecture based on the boundaries. The debug data is correlated with the boundaries of the machine learning design based on the metadata.
    Type: Application
    Filed: December 30, 2024
    Publication date: July 2, 2026
    Applicant: Xilinx, Inc.
    Inventors: Tharun Kumar Ksheerasagar, Hemant Kashyap, Sadanand Mutyala, Rajesh Palla, Prashant Malladi, Pratyush Ranjan, Anurag Dubey, Amit Kasat, Jason Richard Villarreal, Nishant Mysore
  • Patent number: 11474826
    Abstract: Some examples described herein relate to a boot image file. In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to compile an application to generate a boot image file. The boot image file is capable of being loaded onto and executed by a programmable device that comprises data processing engines (DPEs). The boot image file has a format comprising a platform loader and manager (PLM) and partitions. The PLM comprises code capable of being executed by a controller of the programmable device to load the partitions onto the programmable device. Each of the partitions comprises a bitstream, executable code, data, or a combination thereof. The partitions collectively include a single global partition that comprises DPE partitions that are capable of being loaded onto one or more of the DPEs.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 18, 2022
    Assignee: XILINX, INC.
    Inventors: Prashant Malladi, Sadanand Mutyala