Patents by Inventor Prashant Mohan Kulkarni

Prashant Mohan Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Row Repair Circuitry
    Publication number: 20250087296
    Abstract: Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 13, 2025
    Inventors: Andy Wangkun Chen, Khushal Gelda, Ramesh Manohar, Teresa Louise Mclaurin, Prashant Mohan Kulkarni
  • Structures and control processes for efficient generation of different test clocking sequences, controls and other test signals in scan designs with multiple partitions, and devices, systems and processes of making
    Patent number: 8438437
    Abstract: A scannable integrated circuit (100) including a functional integrated circuit (P1, P2) having scan chains, multiple scan decompressors (120.1, 120.2), each operable to supply scan bits to some of the scan chains (101.k, 102.k), a shared scan-programmable control circuit (110, 300), a tree circuit (400) coupled with the functional integrated circuit (P1, P2), the shared scan-programmable control circuit (110, 300) coupled to control the tree circuit (400), and a selective coupling circuit (180) operable to provide selective coupling with the shared scan-programmable control circuit (110, 300) for scan programming through any of the multiple scan decompressors (120.1, 120.2). Other circuits, devices, systems, and processes of operation and manufacture are disclosed.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: May 7, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Arvind Jain, Prashant Mohan Kulkarni, Srinivas Kumar Vooka, Sundarrajan Subramanian, Rubin Ajit Parekhji
  • STRUCTURES AND CONTROL PROCESSES FOR EFFICIENT GENERATION OF DIFFERENT TEST CLOCKING SEQUENCES, CONTROLS AND OTHER TEST SIGNALS IN SCAN DESIGNS WITH MULTIPLE PARTITIONS, AND DEVICES, SYSTEMS AND PROCESSES OF MAKING
    Publication number: 20120030532
    Abstract: A scannable integrated circuit (100) including a functional integrated circuit (P1, P2) having scan chains, multiple scan decompressors (120.1, 120.2), each operable to supply scan bits to some of the scan chains (101.k, 102.k), a shared scan-programmable control circuit (110, 300), a tree circuit (400) coupled with the functional integrated circuit (P1, P2), the shared scan-programmable control circuit (110, 300) coupled to control the tree circuit (400), and a selective coupling circuit (180) operable to provide selective coupling with the shared scan-programmable control circuit (110, 300) for scan programming through any of the multiple scan decompressors (120.1, 120.2). Other circuits, devices, systems, and processes of operation and manufacture are disclosed.
    Type: Application
    Filed: November 3, 2010
    Publication date: February 2, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Arvind Jain, Prashant Mohan Kulkarni, Srinivas Kumar Vooka, Sundarrajan Subramanian, Rubin Ajit Parekhji