Patents by Inventor Prashant Nair

Prashant Nair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240089027
    Abstract: Computer-implemented systems and methods for Forward Error Correction (FEC) at the IP-Layer with adaptive bandwidth overhead minimization in a packet transmission network, the system including an FEC encoder to process IP packets and generate FEC encoded packets and repair packets, an FEC decoder to receive and process the FEC encoded packets and repair packets, and an FEC controller that includes a set of computer-implemented instructions to carry out functions including configuring an FEC algorithm to control FEC encoding and decoding, packet recovery, and retrieve packet transmission statistics, determining if network bandwidth overhead needs adjustment, controlling tuning parameters, and implementing predictive analysis based at least in part on historic data.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Applicant: CradlePoint, Inc.
    Inventors: Natarajan Venkataraman, Prashant Pai, Deepak Nair
  • Publication number: 20240082394
    Abstract: Provided herein are methods of treating cancer by administering to a subject having cancer an antibody, or functional fragment or functional variant thereof, that specifically binds programmed cell death protein 1 (PD1); and a fusion protein that comprises a targeting moiety and an immunomodulatory moiety, wherein: i) said targeting moiety specifically binds epidermal growth factor receptor (EGFR); and (ii) said immunomodulatory moiety comprises an amino acid sequence of the extracellular domain of transforming growth factor-beta receptor II (TGF?RII).
    Type: Application
    Filed: December 15, 2021
    Publication date: March 14, 2024
    Inventors: Shivakumar Bhadravathi MARIGOWDA, Madhukara A R, Prashant Kumar PANDEY, Srinivas Reddy BOREDDY, Pradip NAIR
  • Patent number: 11481158
    Abstract: Various embodiments are provided for enabling data compression in a computing system by a processor. Each storage block of a storage device associated with a queue may be split. Compression of data may be activated upon data occupancy within a queue exceeding a dynamic threshold. In one aspect, only a partial amount of the data is fetched, back to back, from a divided storage block in the storage block according to the queue based upon the data occupancy within the queue exceeding the dynamic threshold. A complete amount of the data may be fetched from the divided storage block in a storage block according to the queue upon the data occupancy within the queue being less than dynamic threshold.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: October 25, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prashant Nair, Seokin Hong, Michael Healy, Bulent Abali, Alper Buyuktosunoglu
  • Publication number: 20200183620
    Abstract: Various embodiments are provided for enabling data compression in a computing system by a processor. Each storage block of a storage device associated with a queue may be split. Compression of data may be activated upon data occupancy within a queue exceeding a dynamic threshold. In one aspect, only a partial amount of the data is fetched, back to back, from a divided storage block in the storage block according to the queue based upon the data occupancy within the queue exceeding the dynamic threshold. A complete amount of the data may be fetched from the divided storage block in a storage block according to the queue upon the data occupancy within the queue being less than dynamic threshold.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 11, 2020
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prashant NAIR, Seokin HONG, Michael HEALY, Bulent ABALI, Alper BUYUKTOSUNOGLU
  • Patent number: 9727241
    Abstract: A processor maintains a count of accesses to each memory page. When the accesses to a memory page exceed a threshold amount for that memory page, the processor sets an indicator for the page. Based on the indicators for the memory pages, the processor manages data at one or more levels of the processor's memory hierarchy.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: August 8, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, David A. Roberts, Mitesh R. Meswani, Mark R. Nutter, John R. Slice, Prashant Nair, Michael Ignatowski
  • Publication number: 20160231933
    Abstract: A processor maintains a count of accesses to each memory page. When the accesses to a memory page exceed a threshold amount for that memory page, the processor sets an indicator for the page. Based on the indicators for the memory pages, the processor manages data at one or more levels of the processor's memory hierarchy.
    Type: Application
    Filed: February 6, 2015
    Publication date: August 11, 2016
    Inventors: Gabriel H. Loh, David A. Roberts, Mitesh R. Meswani, Mark R. Nutter, John R. Slice, Prashant Nair, Michael Ignatowski