Patents by Inventor Prashant Phatak
Prashant Phatak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120305878Abstract: A nonvolatile memory element may include, but is not limited to: a first electrode; a second electrode; and a resistive switching material disposed between the first electrode and the second electrode, wherein at least one of the first electrode or the second electrode includes at least one of a metal cation or metalloid cation having a valence state, oxidation state or oxidation number and wherein the resistive switching material includes at least one of a metal cation or a metalloid cation having the same valence state oxidation state or oxidation number as the at least one of a metal cation or metalloid cation of the at least one of the first electrode or the second electrode.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: INTERMOLECULAR, INC.Inventors: Michael Miller, Prashant Phatak, Tony Chiang
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Patent number: 8318534Abstract: Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.Type: GrantFiled: May 2, 2011Date of Patent: November 27, 2012Assignee: Intermolecular, Inc.Inventors: Alexander Gorer, Prashant Phatak, Tony Chiang, Igor Ivanov
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Publication number: 20120286230Abstract: Confinement techniques for non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. A resistive switching memory element described herein includes a first electrode adjacent to an interlayer dielectric, a spacer over at least a portion of the interlayer dielectric and over a portion of the first electrode and a metal oxide layer over the spacer and the first electrode such that an interface between the metal oxide layer and the electrode is smaller than a top surface of the electrode.Type: ApplicationFiled: July 30, 2012Publication date: November 15, 2012Applicant: Intermolecular, Inc.Inventor: Prashant Phatak
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Patent number: 8298891Abstract: A resistive-switching memory element is described. The memory element includes a first electrode, a porous layer over the first electrode including a point defect embedded in a plurality of pores of the porous layer, and a second electrode over the porous layer, wherein the nonvolatile memory element is configured to switch between a high resistive state and a low resistive state.Type: GrantFiled: October 21, 2009Date of Patent: October 30, 2012Assignee: Intermolecular, Inc.Inventors: Tony Chiang, Prashant Phatak, Chi-I Lang
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Patent number: 8294242Abstract: Confirment techniques for non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. A resistive switching memory element described herein includes a first electrode adjacent to an interlayer dielectric, a spacer over at least a portion of the interlayer dielectric and over a portion of the first electrode and a metal oxide layer over the spacer and the first electrode such that an interface between the metal oxide layer and the electrode is smaller than a top surface of the electrode.Type: GrantFiled: May 2, 2011Date of Patent: October 23, 2012Assignee: Intermolecular, Inc.Inventor: Prashant Phatak
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Publication number: 20120256155Abstract: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).Type: ApplicationFiled: September 30, 2011Publication date: October 11, 2012Applicant: INTERMOLECULAR, INC.Inventors: Wayne French, Pragati Kumar, Prashant Phatak, Tony Chiang
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Patent number: 8274066Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.Type: GrantFiled: October 4, 2011Date of Patent: September 25, 2012Assignee: Intermolecular, Inc.Inventors: Michael Miller, Prashant Phatak, Tony Chiang, Xiyang Chen, April Schricker, Tanmay Kumar
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Publication number: 20120205610Abstract: A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.Type: ApplicationFiled: April 24, 2012Publication date: August 16, 2012Applicant: Intermolecular Inc.Inventors: Prashant Phatak, Tony Chiang, Michael Miller, Wen Wu
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Publication number: 20120149137Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.Type: ApplicationFiled: February 17, 2012Publication date: June 14, 2012Applicant: Intermolecular, IncInventors: Gaurav Verma, Kurt Weiner, Prashant Phatak, Imran Hashim, Sandra Malhotra, Tony Chiang
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Patent number: 8183553Abstract: A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.Type: GrantFiled: October 29, 2009Date of Patent: May 22, 2012Assignee: Intermolecular, Inc.Inventors: Prashant Phatak, Tony Chiang, Michael Miller, Wen Wu
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Publication number: 20120088328Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.Type: ApplicationFiled: December 17, 2011Publication date: April 12, 2012Applicant: Intermolecular, Inc.Inventors: Prashant Phatak, Tony Chiang, Pragati Kumar, Michael Miller
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Patent number: 8143619Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.Type: GrantFiled: October 15, 2010Date of Patent: March 27, 2012Assignee: Intermolecular, Inc.Inventors: Gaurav Verma, Kurt Weiner, Prashant Phatak, Imran Hashim, Sandra Malhotra, Tony Chiang
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Patent number: 8129704Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.Type: GrantFiled: October 21, 2008Date of Patent: March 6, 2012Assignee: Intermolecular, Inc.Inventors: Prashant Phatak, Tony Chiang, Pragati Kumar, Michael Miller
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Publication number: 20120044751Abstract: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.Type: ApplicationFiled: November 1, 2011Publication date: February 23, 2012Applicant: Intermolecular, Inc.Inventors: Yun Wang, Prashant Phatak, Tony Chiang
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Publication number: 20120032133Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.Type: ApplicationFiled: October 4, 2011Publication date: February 9, 2012Applicant: INTERMOLECULAR, INC.Inventors: Michael Miller, Prashant Phatak, Tony Chiang, Xiying Chen, April Schricker, Tanmay Kumar
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Publication number: 20120025164Abstract: According to various embodiments, a variable resistance memory element and memory element array that uses variable resistance changes includes a select device, such as an ovonic threshold switch. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element.Type: ApplicationFiled: October 4, 2011Publication date: February 2, 2012Applicant: INTERMOLECULAR, INC.Inventors: Wim Deweerd, Yun Wang, Prashant Phatak, Tony Chiang
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Publication number: 20120001148Abstract: A resistance-change memory device using stress engineering is described, including a first layer including a first conductive electrode, a second layer above the first layer including a resistive-switching element, a third layer above the second layer including a second conductive electrode, where a first stress is created in the switching element at a first interface between the first layer and the second layer upon heating the memory element, and where a second stress is created in the switching element at a second interface between the second layer and the third layer upon the heating.Type: ApplicationFiled: September 15, 2011Publication date: January 5, 2012Applicant: INTERMOLECULAR, INC.Inventors: Michael Miller, Prashant Phatak, Tony Chiang
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Patent number: 8072795Abstract: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.Type: GrantFiled: October 28, 2009Date of Patent: December 6, 2011Assignee: Intermolecular, Inc.Inventors: Yun Wang, Prashant Phatak, Tony Chiang
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Patent number: 8062918Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.Type: GrantFiled: December 29, 2008Date of Patent: November 22, 2011Assignee: Intermolecular, Inc.Inventors: Michael Miller, Prashant Phatak, Tony Chiang, Xiying Chen, April Schricker, Tanmay Kumar
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Patent number: 8053364Abstract: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g.Type: GrantFiled: October 1, 2008Date of Patent: November 8, 2011Assignee: Intermolecular, Inc.Inventors: Wayne French, Pragati Kumar, Prashant Phatak, Tony Chiang