Patents by Inventor Prashant Sethi
Prashant Sethi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11768791Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.Type: GrantFiled: May 2, 2022Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: David J. Harriman, Reuven Rozic, Maxim Dan, Prashant Sethi, Robert E. Gough, Shanthanand Kutuva Rabindranath
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Publication number: 20230103000Abstract: Embodiments of apparatuses, methods, and systems for hardware manage address translation services are described. In an embodiment, an apparatus includes a first interconnect, a second interconnect, address translation hardware, a device, a translation lookaside buffer. The address translation hardware is coupled to the interconnect and is to provide a translation of a first address to a second address. The device is coupled to the first interconnect and the second interconnect and is to provide the first address to the address translation hardware through the first interconnect. The translation lookaside buffer includes an entry to store the translation, which is to be provided to the translation lookaside buffer through the first interconnect by the address translation hardware. The device is to access a system memory through the second interconnect using the second address from the entry in the translation lookaside buffer.Type: ApplicationFiled: September 25, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Rupin Vakharwala, Prashant Sethi, Rajesh M. Sankaran, Philip R. Lantz, David J. Harriman, Utkarsh Y. Kakaiya, Vinay Raghav, Ashok Raj, Siva Bhanu Krishna Boga
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Patent number: 11513808Abstract: Automatic-switching and deployment of software (SW)- or firmware (FW)-based USB4 connection managers (CMs) and associated methods, apparatus, software and firmware. A handshake is defined between BIOS and an operating system (OS) to discover supported CM capability and dynamically switch from a FW CM to a SW CM and visa verse if there is a mismatch. In addition, a mechanism is defined to deploy the correct FW or SW CM driver based on class code, 2-part or 4-part ID. Support for continued USB4 operation during an OS upgrade or downgrade is provided, while ensuring that the best possible CM solution is used based on the advertised platform and OS capability. USB4 controllers support a pass-through mode under which the host controller FW redirects control packets sent between an SW CM and a USB4 fabric, and a FW CM mode under which control packets are communicated between the host controller FW and the USB4 fabric to configure USB4 peripheral devices and/or USB4 hubs in the USB4 fabric.Type: GrantFiled: June 28, 2019Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Vinay Raghav, Prashant Sethi, Robert Gough, Reuven Rozic, Uri Soloveychik
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Publication number: 20220334994Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.Type: ApplicationFiled: May 2, 2022Publication date: October 20, 2022Applicant: Intel CorporationInventors: David J. Harriman, Reuven Rozic, Maxim Dan, Prashant Sethi, Robert E. Gough, Shanthanand Kutuva Rabindranath
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Patent number: 11461098Abstract: Systems, methods, and apparatuses relating to an instruction for operating system transparent instruction state management of new instructions for application threads are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, and an execution circuit to execute the decoded single instruction to cause a context switch from a current state to a state comprising additional state data that is not supported by an execution environment of an operating system that executes on the hardware processor.Type: GrantFiled: June 27, 2020Date of Patent: October 4, 2022Assignee: Intel CorporationInventors: Toby Opferman, Prashant Sethi, Abhimanyu K. Varde, Barry E. Huntley, Michael W. Chynoweth, Jason W. Brandt
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Patent number: 11321264Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.Type: GrantFiled: December 29, 2020Date of Patent: May 3, 2022Assignee: INTEL CORPORATIONInventors: David J. Harriman, Reuven Rozic, Maxim Dan, Prashant Sethi, Robert E. Gough, Shanthanand Kutuva Rabindranath
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Publication number: 20220075661Abstract: Technologies for scheduling acceleration in a pool of accelerator devices include a compute device. The compute device includes a compute engine to execute an application. The compute device also includes an accelerator pool including multiple accelerator devices. Additionally, the compute device includes an acceleration scheduler logic unit to obtain, from the application, a request to accelerate a function, determine a capacity of each accelerator device in the accelerator pool, schedule, in response to the request and as a function of the determined capacity of each accelerator device, acceleration of the function on one or more of the accelerator devices to produce output data, and provide, to the application and in response to completion of acceleration of the function, the output data to the application. Other embodiments are also described and claimed.Type: ApplicationFiled: November 15, 2021Publication date: March 10, 2022Inventors: Hamesh PATEL, Aniket A. BORKAR, Prashant SETHI, Deviusha KRISHNAMOORTHY
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Publication number: 20210406019Abstract: Systems, methods, and apparatuses relating to an instruction for operating system transparent instruction state management of new instructions for application threads are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, and an execution circuit to execute the decoded single instruction to cause a context switch from a current state to a state comprising additional state data that is not supported by an execution environment of an operating system that executes on the hardware processor.Type: ApplicationFiled: June 27, 2020Publication date: December 30, 2021Inventors: TOBY OPFERMAN, PRASHANT SETHI, ABHIMANYU K. VARDE, BARRY E. HUNTLEY, MICHAEL W. Chynoweth, JASON W. BRANDT
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Publication number: 20210318971Abstract: An example compute node is disclosed that includes a plurality of processor cores. The example further includes an operating system (OS) having an OS power management (OSPM) engine to determine that a first of the plurality of processor cores has entered an idle state; and a system management mode (SMM) handler to detect a system management interrupt (SMI) and transition control of hardware resources of the first processor core from the OS to a basic input output system (BIOS) to enter a system management mode (SMM) in order to perform one or more platform management operations.Type: ApplicationFiled: March 22, 2021Publication date: October 14, 2021Inventors: Gaurav Khanna, Prashant Sethi, Venkatesh Ramamurthy
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Publication number: 20210232522Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.Type: ApplicationFiled: December 29, 2020Publication date: July 29, 2021Applicant: Intel CorporationInventors: David J. Harriman, Reuven Rozic, Maxim Dan, Prashant Sethi, Robert E. Gough, Shanthanand Kutuva Rabindranath
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Patent number: 10956345Abstract: A method is described. The method includes determining that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state, triggering a SMI for the first processor core, the first processor core entering a system management mode (SMM) and performing one or more platform management operations.Type: GrantFiled: April 1, 2016Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Gaurav Khanna, Prashant Sethi, Venkatesh Ramamurthy
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Patent number: 10877915Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.Type: GrantFiled: September 30, 2016Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: David J. Harriman, Reuven Rozic, Maxim Dan, Prashant Sethi, Robert E. Gough, Shanthanand Kutuva Rabindranath
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Patent number: 10754808Abstract: Bridge logic is provided to receive a request from a device, where the request references an address of a secondary address space. The secondary address space corresponds to a subset of addresses in a configuration address space of a system, and the secondary address space corresponds to a first view of the configuration address space. The bridge logic uses a mapping table to translate the address into a corresponding address in the configuration address space, where addresses of the configuration address space correspond to a different second view of the configuration address space.Type: GrantFiled: December 20, 2015Date of Patent: August 25, 2020Assignee: Intel CorporationInventors: Prashant Sethi, Michael T. Klinglesmith, David J. Harriman, Reuven Rozic, Shanthanand Kutuva Rabindrananth
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Patent number: 10691612Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.Type: GrantFiled: October 12, 2018Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Brent S. Baxter, Clifford D. Hall, Prashant Sethi, William H. Clifford
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Patent number: 10642665Abstract: Particular embodiments described herein provide for an electronic device that can receive data from an operating system in an electronic device, where the data is related to hardware that is in communication with the electronic device through a multimodal interface and communicate the data and/or related data to a local policy manager, where the local policy manager is in communication with the multimodal interface. The multimodal interface can be configured to support power transfers, directionality, and multiple input/output (I/O) protocols on the same interface.Type: GrantFiled: March 21, 2016Date of Patent: May 5, 2020Assignee: Intel CorporationInventors: Peter S. Adamson, Nivedita Aggarwal, Karunakara Kotary, Abdul Rahman Ismail, Tin-Cheung Kung, David T. Hines, Chia-Hung Sophia Kuo, Ajay V. Bhatt, Karthi R. Vadivelu, Prashant Sethi
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Patent number: 10628367Abstract: Examples include techniques for dynamically modifying a platform form factor of a mobile device. In some examples, a system may include a split memory array having a first memory within a docking system and a second memory element within a small form factor (SFF) mobile device. A platform form factor determination component may dynamically select between multiple platform form factors based on a determination that the SFF mobile device is coupled with the docking system. An interface logic component may access the first memory storage of the docking system during a memory (e.g., graphics) computation when the mobile device is physically and electrically/communicably coupled with the docking system to allow the SFF mobile device to have full LFF functionality. When the SFF mobile device is disconnected from the docking system, the interface logic component may access only the second memory storage of the SFF mobile device to provide SFF functionality.Type: GrantFiled: December 28, 2016Date of Patent: April 21, 2020Assignee: INTEL CORPORATIONInventors: Tawfik M. Rahal-Arabi, Prashant Sethi, Anthony M. Constantine, Yu-Liang Shiao, Chang-Wu Yen
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Patent number: 10585721Abstract: Particular embodiments described herein provide for an electronic device that can receive data from an operating system in an electronic device, where the data is related to hardware that is in communication with the electronic device through a multimodal interface and communicate the data and/or related data to a local policy manager, where the local policy manager is in communication with the multimodal interface. The multimodal interface can be configured to support power transfers, directionality, and multiple input/output (I/O) protocols on the same interface.Type: GrantFiled: March 21, 2016Date of Patent: March 10, 2020Assignee: Intel CorporationInventors: Peter S. Adamson, Nivedita Aggarwal, Karunakara Kotary, Abdul Rahman Ismail, Tin-Cheung Kung, David T. Hines, Chia-Hung Sophia Kuo, Ajay V. Bhatt, Karthi R. Vadivelu, Prashant Sethi
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Patent number: 10521386Abstract: Various techniques for enabling the control and monitoring of a USB device mode controller to a USB-C connector, for the performance of a USB device mode data connection, are disclosed herein. In an example, a computing system that includes multiple USB-C connectors but a single USB device mode controller may manage the availability of the controller to a particular connector. The computing system may determine availability of a USB device mode controller to control the first USB-C connector, wherein the attempted data connection occurs with the first USB-C connector configured as an upstream facing port. The computing system may further perform, in response, a data role swap of the first USB-C connector to configure the first USB-C connector as a downstream facing port. The computing system may, further continue the attempted data connection with the remote computing system via the first USB-C connector configured as a downstream facing port.Type: GrantFiled: August 23, 2018Date of Patent: December 31, 2019Assignee: Intel CorporationInventors: Vijaykumar B. Kadgi, Tin-Cheung Kung, Nivedita Aggarwal, Chia-Hung Kuo, Prashant Sethi
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Patent number: 10509729Abstract: Embodiments of an invention for address translation for scalable I/O device virtualization are disclosed. In one embodiment, an apparatus includes PASID table lookup circuitry. The PASID table lookup circuitry is to find a PASID-entry in a PASID table. The PASID-entry is to include a PASID processing mode (PPM) indicator and a first pointer to a first translation structure. The PPM indicator is to specify one of a plurality of translation types, the one of the plurality of translation types to use the first translation structure.Type: GrantFiled: January 13, 2016Date of Patent: December 17, 2019Assignee: Intel CorporationInventors: Rajesh M Sankaran, Randolph L Campbell, Prashant Sethi, David J Harriman
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Patent number: 10452403Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.Type: GrantFiled: September 26, 2015Date of Patent: October 22, 2019Assignee: Intel CorporationInventors: Hong Wang, John P. Shen, Edward T. Grochowski, Richard A. Hankins, Gautham N. Chinya, Bryant E. Bigbee, Shivnandan D. Kaushik, Xiang Chris Zou, Per Hammarlund, Scott Dion Rodgers, Xinmin Tian, Anil Aggawal, Prashant Sethi, Baiju V. Patel, James P Held