Abstract: A method is described that comprises uses at least a portion of a configuration transaction address to perform a look-up into a memory. The configuration transaction is to perform a configuration function at an I/O Unit connected to an I/O segment within a link-based computing system. The look-up is to identify a component within the link-based computing system. The I/O segment is accessed through the component within the link-based computing system.

Abstract: Techniques for selectively forwarding interrupt signals to virtual machines.

Abstract: The ability to configure an integrated device with a decoder in a processor or network component according to PCI or PCI Express interconnects.

Abstract: A system includes a direct memory access (DMA) engine to move data on a real time basis and a communication front-end to transmit and receive the data. In another embodiment, the system may also include a medium access control (MAC) to control transmission and reception of the data and that may be partitioned or divided according to response times to carry out selected functions.

Abstract: A method for accessing a configuration data space for a device connected to a processor through an interconnect includes receiving a request from the processor to access the processor's addressable space. The request is generated in response to receiving an instruction intended to access the device's configuration data space. A map between the device's configuration data space and the processor's addressable space is accessed, the map having previously mapped the device's configuration data space to one or more pages of the processor's addressable space. Using the map, the request from the processor is translated into a configuration cycle on the interconnect to access the device's configuration data space.

Abstract: A system includes a direct memory access (DMA) engine to move data on a real time basis and a communication front-end to transmit and receive the data. In another embodiment, the system may also include a medium access control (MAC) to control transmission and reception of the data and that may be partitioned or divided according to response times to carry out selected functions.

Abstract: A system having an I/O interconnect topology utilizes internal packetized communications. The system includes a host system element, a plurality of switching elements, and a root complex to bridge communications between the host system and the switching elements. The ports of at least some of the switching elements have a cross-link device associated therewith, which is a logical device defined by configuration space of the switching element. Each cross-link device defines a cross-link communication path between two switching elements of the hierarchy allowing communications between peripherals to bypass the host.

Abstract: Memory is allocated for use by a graphics processor. Available portions of system memory are identified by requesting an amount of system memory from an operating system and receiving locations of the available portions from the operating system. Those available portions are then allocated for use by the graphics processor.

Abstract: A method and apparatus for communicating general purpose events in-band from a downstream controller is presented.

Abstract: A system includes a direct memory access (DMA) engine to move data on a real time basis and a communication front-end to transmit and receive the data. In another embodiment, the system may also include a medium access control (MAC) to control transmission and reception of the data and that may be partitioned or divided according to response times to carry out selected functions.

Abstract: A method and apparatus for updating control data for a device driver that is stored on a first non-volatile memory. New driver control data is written to a second non-volatile memory.

Abstract: A method for accessing a configuration data space for a device connected to a processor through an interconnect includes receiving a request from the processor to access the processor's addressable space. The request is generated in response to receiving an instruction intended to access the device's configuration data space. A map between the device's configuration data space and the processor's addressable space is accessed, the map having previously mapped the device's configuration data space to one or more pages of the processor's addressable space. Using the map, the request from the processor is translated into a configuration cycle on the interconnect to access the device's configuration data space.

Abstract: A method for assigning a device to a first virtual machine includes connecting the device, directly or indirectly, to a computer through an interconnect. The first virtual machine and a second virtual machine are run on the computer. The device is assigned to the first virtual machine for exclusive use by the first virtual machine, and the assignment is enforced.

Abstract: Control data for a device driver that is stored on a first non-volatile memory is updated by writing new driver control data to a second non-volatile memory. In an embodiment, the new driver control data may be stored on the second non-volatile memory without modifying the control data on the first non-volatile memory. In a further embodiment, a processor reads non-volatile from the first non-volatile memory into a system memory, reads supplemental driver control data from the second non-volatile memory, and updates the set of driver control data in the system memory based on the supplemental driver control data.

Abstract: Memory is allocated for use by a graphics processor. Available portions of system memory are identified by requesting an amount of system memory from an operating system and receiving locations of the available portions from the operating system. Those available portions are then allocated for use by the graphics processor based at least in part on the devices in which the available portions are located.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: A size of a tile of memory is determined, where a tile is a segment of the memory having a dimension that is less than a pitch of the memory. Data is then stored in the tile. To access the data, a graphics processor obtains an indication (from a configuration register) that the memory is tiled, and accesses the data stored in the tile before accessing other segments of the memory.

Abstract: A method and apparatus for managing memory used by a device driver in an operating system. The method comprises: (i) configuring a chipset to set up a mapping table for memory address translation, (ii) allocating a device memory in response to a request by the device driver, and (iii) mapping non-contiguous system memory to contiguous device memory using the mapping table.

Abstract: A method and apparatus for managing memory used by a device driver in an operating system. The method comprises: (i) configuring a chipset to set up a mapping table for memory address translation, (ii) allocating a device memory in response to a request by the device driver, and (iii) mapping non-contiguous system memory to contiguous device memory using the mapping table.