Patents by Inventor Prashant Shamarao

Prashant Shamarao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160195957
    Abstract: In an example, a processing system for an integrated display device and capacitive sensing device includes driver circuitry and a driver module. The driver circuitry is configured for coupling to a plurality of source lines and a plurality of sensor electrodes, where each of the plurality of sensor electrodes comprises at least one common electrode configured for display updating and capacitive sensing. The driver module is coupled to the driver circuitry and configured to drive the plurality of sensor electrodes for capacitive sensing during a first non-display update period that occurs between first and second display line update periods of a display frame, where the non-display update period is at least as long as one of the first and second display line update periods. The driver module is further configured to operate each of the plurality of source lines to reduce display artifacts during the non-display update period.
    Type: Application
    Filed: June 30, 2015
    Publication date: July 7, 2016
    Inventors: Joseph Kurth REYNOLDS, Stephen L. MOREIN, Prashant SHAMARAO
  • Publication number: 20160195947
    Abstract: In one embodiment, a system includes one or more source drivers operable to drive a portion of a row or column of a display. The system also includes a timing controller coupled to each of the one or more source drivers and configured to control the one or more source drivers. The system further includes a downstream link for each of the one or more source drivers, configured to transfer data from the timing controller to one of the one or more source drivers. The system also includes an upstream link for each of the one or more source drivers, configured to transfer uplink data from one of the one or more source drivers to the timing controller, wherein the uplink data includes at least one of downlink lock status information and touch data.
    Type: Application
    Filed: June 26, 2015
    Publication date: July 7, 2016
    Inventors: Stephen L. MOREIN, Prashant SHAMARAO, Zhibing LIU
  • Patent number: 9323698
    Abstract: A data transmission system is provided. The data transmission system includes a source device having a source device controller and a register and a sink device having a sink device controller. The data transmission system also includes a transmission link coupling the source device and the sink device. The transmission link includes a unidirectional main line having a plurality of main link channels, a bidirectional auxiliary line configured to transmit data between the source device and the sink device at a first data rate, and a unidirectional interrupt line. The transmission link is configured to transmit data from the source device to the sink device over one of the main link lines at a second data rate and to transmit data from the sink device to the source device over the auxiliary line at the second data rate. The transmission link may comply with the DisplayPort standard, and the data may be transmitted in accordance with the USB standard.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: April 26, 2016
    Assignee: Synaptics Incorporated
    Inventors: Ji Park, Prashant Shamarao
  • Publication number: 20160094225
    Abstract: A method for converting data signals from one power supply voltage domain for use in another power supply voltage domain. The method includes receiving the data signal at a first node of the integrated circuit, wherein the first node is within the first power supply voltage domain. The method also includes generating a first intermediate differential signal from the data signal via a first conversion circuit of the integrated circuit. The method further includes communicating the first intermediate differential signal to a first cross-coupled latch, wherein the first cross-coupled latch generates a first output signal based on the first intermediate differential signal. The method also includes outputting the first output signal from a second node of the integrated circuit, wherein the second node is in the second power supply voltage domain. Other embodiments, such as an integrated circuit, and an input device, are also provided.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Inventors: Shao-Jen LIM, Prashant SHAMARAO
  • Patent number: 8686759
    Abstract: An AUX channel amplifier for amplifying data in the AUX channel of a Display Port device. In some embodiments, the amplifier includes a first amplifier coupled to amplify a signal from a source to a sink and a second amplifier coupled to amplify a signal from the sink to the source. A slicer can be utilized to digitize the signal from the source. In some embodiments, a clock and data recovery can be utilized to receive signals from the source and a second clock and data recovery can be utilized to receive signals from the sink. A controller determine the direction of data flow and enables the first amplifier or the second amplifier accordingly.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: April 1, 2014
    Assignee: Synaptics Incorporated
    Inventors: Prashant Shamarao, Chris DeMarco, Rohit Singhal, Robert Bishop, Alex Reed
  • Patent number: 8432408
    Abstract: Rate matching for use in data links between a source device and a sink device is provided. A rate matching device includes a first-in-first-out (FIFO) buffer having a write pointer and a read pointer; a write control having a write clock to write an input data stream from the source device onto the FIFO buffer using the write pointer; a read control having a read clock to read data from the FIFO buffer using a read pointer, insert data to an output data stream and transmitting the data stream to the sink device; a processor to provide a bit number based on the write clock period and the read clock period, wherein the read control inserts blanking data into the output data stream while the read pointer is stopped in the FIFO buffer to allow the write pointer to move ahead by the bit number provided by the processor. Some embodiments are thus able to avoid buffer overflow or underflow scenarios.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: April 30, 2013
    Assignee: Synaptics Incorporated
    Inventor: Prashant Shamarao
  • Publication number: 20130083047
    Abstract: A system for buffering a video signal is provided. The system includes a graphics processing unit (GPU), the GPU generating the video signal, and a buffering circuit coupled to the GPU, the buffering circuit receiving and temporarily storing the video signal when the GPU enters a power saving mode. The system also includes a display device coupled to the bridge circuit and receiving the video signal from the buffering circuit. The buffering circuit includes an internal memory device configured to temporarily store a first portion of the video signal, and an external memory device configured to temporarily store a second portion of the video signal. A circuit and method for buffering a video signal are also provided.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Inventors: Prashant SHAMARAO, Rohit Singhal
  • Publication number: 20130080665
    Abstract: A data transmission system is provided. The data transmission system includes a source device having a source device controller and a register and a sink device having a sink device controller. The data transmission system also includes a transmission link coupling the source device and the sink device. The transmission link includes a unidirectional main line having a plurality of main link channels, a bidirectional auxiliary line configured to transmit data between the source device and the sink device at a first data rate, and a unidirectional interrupt line. The transmission link is configured to transmit data from the source device to the sink device over one of the main link lines at a second data rate and to transmit data from the sink device to the source device over the auxiliary line at the second data rate. The transmission link may comply with the DisplayPort standard, and the data may be transmitted in accordance with the USB standard.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Inventors: Ji PARK, Prashant SHAMARAO
  • Publication number: 20110249192
    Abstract: Rate matching for use in data links between a source device and a sink device is provided. A rate matching device includes a first-in-first-out (FIFO) buffer having a write pointer and a read pointer; a write control having a write clock to write an input data stream from the source device onto the FIFO buffer using the write pointer; a read control having a read clock to read data from the FIFO buffer using a read pointer, insert data to an output data stream and transmitting the data stream to the sink device; a processor to provide a bit number based on the write clock period and the read clock period, wherein the read control inserts blanking data into the output data stream while the read pointer is stopped in the FIFO buffer to allow the write pointer to move ahead by the bit number provided by the processor. Some embodiments are thus able to avoid buffer overflow or underflow scenarios.
    Type: Application
    Filed: April 7, 2010
    Publication date: October 13, 2011
    Inventor: Prashant Shamarao
  • Patent number: 7911261
    Abstract: A substrate biasing circuit may include a first pump control circuit that generates a first control signal in response to a first reference voltage and a voltage of a first substrate portion, and includes a first reference generator coupled between a temperature compensated voltage and a reference power supply voltage that varies the first reference voltage in response to the voltage of the first substrate voltage and the temperature compensated voltage. A first clamp circuit may generate a first clamp signal in response to a first limit voltage and the voltage of the first substrate portion, the first limit voltage being a scaled version of the temperature compensated voltage. A first charge pump may pump the first substrate portion in at least a first voltage direction in response to the first control signal, and is prevented from pumping in the first voltage direction in response to the first clamp signal.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: March 22, 2011
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Prashant Shamarao
  • Publication number: 20110032006
    Abstract: An AUX channel amplifier for amplifying data in the AUX channel of a Display Port device. In some embodiments, the amplifier includes a first amplifier coupled to amplify a signal from a source to a sink and a second amplifier coupled to amplify a signal from the sink to the source. A slicer can be utilized to digitize the signal from the source. In some embodiments, a clock and data recovery can be utilized to receive signals from the source and a second clock and data recovery can be utilized to receive signals from the sink. A controller determine the direction of data flow and enables the first amplifier or the second amplifier accordingly.
    Type: Application
    Filed: February 24, 2010
    Publication date: February 10, 2011
    Inventors: PRASHANT SHAMARAO, Chris Demarco, Rohit Singhal, Robert Bishop, Alex Reed
  • Patent number: 7555668
    Abstract: A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: June 30, 2009
    Assignee: Integrated Device Technology, Inc.
    Inventors: Paul Joseph Murtagh, Prashant Shamarao, Alejandro Flavio Gonzalez
  • Patent number: 7548105
    Abstract: A method and apparatus for source synchronous testing have been disclosed. In one case a data signal is delayed and a selectively activated delay is applied to a clock. This allows the clock to be positioned before the data and also after the data.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: June 16, 2009
    Assignee: Integrated Device Technology, inc
    Inventors: Robert W. Shrank, Moussa Sobaiti, Prashant Shamarao, Brian Butka, Jim K. Harris
  • Patent number: 7447812
    Abstract: Multi-queue first-in first-out (FIFO) memory devices include multi-port register files that provide write count and read count flow-through when the write and read queues are equivalent. According to some of these embodiments, a multi-queue FIFO memory device includes a write flag counter register file that is configured to support flow-through of write counter updates to at least one read port of the write flag counter register file. This flow-through occurs when an active write queue and an active read queue within the FIFO memory device are the same. A read flag counter register file is also provided, which supports flow-through of read counter updates to at least one read port of the read flag counter register file when the active write queue and the active read queue are the same.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: November 4, 2008
    Assignee: Integrated Device Technology, Inc.
    Inventors: Jason Zhi-Cheng Mo, Prashant Shamarao, Jianghui Su
  • Publication number: 20080022145
    Abstract: A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.
    Type: Application
    Filed: July 18, 2006
    Publication date: January 24, 2008
    Inventors: Paul Joseph Murtagh, Prashant Shamarao, Alejandro Flavio Gonzalez
  • Publication number: 20060294411
    Abstract: A method and apparatus for source synchronous testing have been disclosed.
    Type: Application
    Filed: March 31, 2006
    Publication date: December 28, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Robert Shrank, Moussa Sobaiti, Prashant Shamarao, Brian Butka, Jim Harris
  • Patent number: 7134034
    Abstract: A data path includes a downstream stage that strobes data at an input thereof responsive to a first control signal, an upstream stage that sends data to the input of the downstream stage responsive to a second control signal, and a control circuit operative to fix timing of the second control signal to timing of the first control signal. The data path may further include a second upstream stage that sends data to an input of the first upstream stage responsive to a third control signal having a timing with respect to the second control signal that varies responsive to a frequency at which data is transferred along the data path. A fixed delay circuit, e.g., a fixed delay circuit in a forward path of a DLL or PLL, may generate the first control signal from the second control signal.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: November 7, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventor: Prashant Shamarao
  • Patent number: 6907479
    Abstract: Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: June 14, 2005
    Assignee: Integrated Device Technology, Inc.
    Inventors: Curt A. Karnstedt, Bruce L. Chin, Prashant Shamarao, Mario Montana
  • Patent number: 6894529
    Abstract: Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively. The second totem pole driver stage has at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively. The linearity of the output driver circuit is enhanced by including a first resistive element that extends between the first and second totem pole driver stages.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: May 17, 2005
    Assignee: Integrated Device Technology, Inc.
    Inventors: Yew-Keong Chong, David J. Klein, XinXin Shao, Prashant Shamarao, Brian K. Butka
  • Publication number: 20030018862
    Abstract: Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially.
    Type: Application
    Filed: August 30, 2001
    Publication date: January 23, 2003
    Inventors: Curt A. Karnstedt, Bruce L. Chin, Prashant Shamarao, Mario Montana