Abstract: Technology is disclosed herein for aborting a tail portion of a command queue in a storage device. In one aspect, one or more control circuits of a storage system are configured to abort tasks at a tail end of a command queue in response to receiving a task tail abort command. However, tasks at the head end of the command queue may still be executed. Thus, the head end of the command queue need not be rebuilt after the task tail abort command is performed. Therefore, considerable time is saved by not having to rebuild the head end of the command queue. Note that the task tail abort command may be received while the storage system is in a sequential command execution mode, in which tasks are executed in the order of their respective task identifiers.

Abstract: Technology is disclosed herein for aborting a tail portion of a command queue in a storage device. In one aspect, one or more control circuits of a storage system are configured to abort tasks at a tail end of a command queue in response to receiving a task tail abort command. However, tasks at the head end of the command queue may still be executed. Thus, the head end of the command queue need not be rebuilt after the task tail abort command is performed. Therefore, considerable time is saved by not having to rebuild the head end of the command queue. Note that the task tail abort command may be received while the storage system is in a sequential command execution mode, in which tasks are executed in the order of their respective task identifiers.

Abstract: A high output voltage VOH level and a low output voltage VOL level parametric test system may include test circuitry coupled to output nodes of input/output (I/O) driver circuits. The test circuitry may source and sink current to the output nodes while the I/O driver circuits are in pull down and pull up states, respectively, in order to generate output voltages on the output nodes. The parametric test system may compare the output voltages with a plurality of high and low reference levels to determine ranges of the output voltages. The ranges may be used to determine whether the I/O driver circuits pass the VOH and VOL test requirements. The VOH/VOL test system may be implemented on-chip with other components of the external device, which may eliminate the need to perform other parametric testing with external test equipment.

Abstract: Methods and circuits for delay compensation are provided. A data clock may be generated from a peripheral clock. Sample data may be provided in a data signal on a bus in response to an edge of the data clock, where the edge of the data clock is triggered by an initial edge of the peripheral clock. A delay of the data clock relative to the peripheral clock may be selected based on a time difference between the initial edge of the peripheral clock and a time at which the sample data is detected on the bus. A delayed data clock having the selected delay relative to the peripheral clock may be generated. Requested data may be provided on the bus in response to an edge of the delayed data clock.

Abstract: Methods and circuits for delay compensation are provided. A data clock may be generated from a peripheral clock. Sample data may be provided in a data signal on a bus in response to an edge of the data clock, where the edge of the data clock is triggered by an initial edge of the peripheral clock. A delay of the data clock relative to the peripheral clock may be selected based on a time difference between the initial edge of the peripheral clock and a time at which the sample data is detected on the bus. A delayed data clock having the selected delay relative to the peripheral clock may be generated. Requested data may be provided on the bus in response to an edge of the delayed data clock.