Abstract: According to one general aspect, an apparatus may include a bit cell configured to store a bit of information. The apparatus may include a first voltage configured to supply the bit cell with power. The apparatus may include a wordline driver configured to cause the bit to be read from the bit cell. The wordline driver may be configured to operate during a read operation at a second voltage that is lower than the first voltage, wherein the second voltage is determined by charge sharing between a plurality of capacitances. The wordline driver may include a switch configured to disconnect the wordline driver from the first voltage before an input word line signal is applied to the wordline driver, and wherein the switch is responsive to a clock signal.

Abstract: Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

Abstract: Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

Abstract: Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.

Abstract: Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

Abstract: A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).

Abstract: Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

Abstract: A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.

Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.

Abstract: Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.

Abstract: A storage unit on an integrated circuit stores information that identifies a circuit on the integrated circuit, a selected operating condition, and a required operating configuration for the circuit for the selected operating condition. The manner of operating the circuit is changed to the required operating configuration in response to an operating condition of the circuit changing to the selected operating condition. This allows for efficiently identifying the few circuits that do not meet specified requirements based on a reduction in, for example, operating voltage, and altering their operation in order to meet the specified requirements relative to the reduced operating voltage without having to do so for the vast majority of the circuits that are able to meet the requirements at the lowered operating voltage.

Abstract: A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.

Abstract: A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).

Abstract: A memory and method for access the memory are provided. A first test is used to test memory elements to determine a lowest power supply voltage at which all the memory elements will operate to determine a weak memory element. Redundancy is used to substitute a redundant memory element for the weak memory element. The weak memory element is designated as a test element. In response to receiving a request to change a power supply voltage provided to the memory elements, a second test is used to test the test element to determine if the test element will function correctly at a new power supply voltage. If the test element passes the second test, the memory elements are accessed at the new power supply voltage. If the test element fails the second test, the memory elements are accessed using an access assist operation.

Abstract: A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased.

Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a third node to couple the first data signal to the third node. The first node is decoupled from the second node and a first step of latching the first data signal at the third node is performed, wherein the first step of latching is through the second node while the second node is coupled to the third node. The second node is decoupled from the third node and a second step of latching is performed wherein the first data signal latched at the third node while the second node is decoupled from the third node.

Abstract: A method of writing data to a selected column of a memory includes selecting a first column. The data writing is initiated by applying a logic high to a first bit line of the first column and a first potential to a second bit line of the first column that is lower than the logic high. The first potential is removed and a second potential is applied to the second bit line. The second potential is less than the first potential. The first potential may be ground, and the second potential may be a negative voltage. Reducing the write voltage for the bit line that is receiving a logic low improves its ability to be written. By first bringing the logic low to the first potential, which may be ground, and then further reducing the applied voltage, the requirements on the source of the second potential are reduced.

Abstract: A memory has a method of operating that includes performing operations of a first type and a second type. A first voltage is coupled to a power supply node of a first memory cell of a memory array during a first operation of the first type. The first voltage is decoupled from the power supply node in response to terminating the first operation of the first type so as to allow the power supply node to drift. If the power supply node drifts to a second voltage, a power supply source is coupled to the power supply node. This is useful in reducing power in the circuit that produces the first voltage.