Abstract: An apparatus for system design verification has a test case module for compiling a test case in a scripting language (such as TCL) and a testbench including the design under test and operating with a Hardware Descriptor Language (such as SystemVerilog). A stimulus generated by the test case module is applied to the testbench through an interface gasket based on ‘C’.

Abstract: An apparatus for system design verification has a test case module for compiling a test case in a scripting language (such as TCL) and a testbench including the design under test and operating with a Hardware Descriptor Language (such as SystemVerilog). A stimulus generated by the test case module is applied to the testbench through an interface gasket based on ‘C’.

Abstract: An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set of transactors sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.

Abstract: An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.