Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

Abstract: Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.

Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

Abstract: Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.

Abstract: Systems, methods, and apparatus for power management are disclosed. A power management integrated circuit has a bus interface circuit configured to couple the power management integrated circuit to a shared communication bus, one or more regulator circuits configured to provide current to a managed device, and a controller. The controller is configured to determine that current consumption by the managed device exceeds a threshold level, generate an extended current level message to be transmitted over the shared communication bus to the managed device and transmit a time value with the extended current level message, the time value indicative of an elapsed time between generation of the extended current level message and start of transmission of the extended current level message.