Patents by Inventor Prashanth Kumar Kakkireni

Prashanth Kumar Kakkireni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250208673
    Abstract: Aspects of the disclosure are directed to active thermal control for a system on a chip (SOC). In accordance with one aspect, an internal fan controller is configured to generate a fan pulse width modulation (PWM) signal, wherein the internal fan controller is integrated as part of a system on a chip (SOC); a fan module is configured to generate one or more tachometer pulses; and an internal tachometer coupled to the internal fan controller and the fan module, the internal tachometer is configured to receive the one or more tachometer pulses from the fan module, wherein the internal tachometer is integrated as part of the system on a chip (SOC).
    Type: Application
    Filed: December 21, 2023
    Publication date: June 26, 2025
    Inventors: Tejas GRANDHI, Prashanth Kumar KAKKIRENI, Tejaswini SHENOY, Venkatesh RAVIPATI
  • Publication number: 20250189385
    Abstract: Communication of thermal states is described for chiplets. An example includes a chiplet and a plurality of chiplet thermal sensors thermally coupled to the chiplet and configured to generate thermal signals in response to a temperature of the chiplet. A chiplet thermal combiner is coupled to the thermal sensors and configured to receive the thermal signals from the thermal sensors, to generate a combined thermal signal in response, and to generate a temperature signal in response to the combined thermal signal. An external connector is coupled to the chiplet thermal combiner and configured to assert the temperature signal to an external component to activate a thermal mitigation.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 12, 2025
    Inventors: Prashanth Kumar KAKKIRENI, Tejas GRANDHI, Ramacharan SUNDARARAMAN, Christophe AVOINNE
  • Publication number: 20250132560
    Abstract: Techniques and apparatus for swapping a primary power source (e.g., a main battery) while using a secondary power source (e.g., a backup battery or a supercapacitor) to power a portable device. One example integrated circuit (IC) for power management generally includes a first power supply node; a second power supply node; a first port for coupling to a primary power source; a first switch coupled between the first power supply node and the first port; a second port for coupling to a secondary power source; a second switch coupled between the first power supply node and the second port; and a third switch coupled between the first and second power supply nodes. For certain aspects, the IC also includes a third power supply node, a voltage regulator coupled between the first and third power supply nodes, and a fourth switch coupled between the second and third power supply nodes.
    Type: Application
    Filed: December 30, 2024
    Publication date: April 24, 2025
    Inventors: Vignesh MARIYAPPAN, Anand Kumar KALAIRAJ, Prashanth Kumar KAKKIRENI, Amit DAS
  • Publication number: 20250103092
    Abstract: A global count or reference time in a computing device may be maintained during a sleep state in which the global counter is powered off. The global count from the global counter may be saved in a register when the sleep state is entered. When the sleep state is exited, the global count in the register may be restored in the global counter.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Inventors: Prashanth Kumar KAKKIRENI, Naveen Kumar NARALA, Amod PHADKE, Arun GOTHEKAR, Anirudh GHAYAL
  • Publication number: 20240322562
    Abstract: Techniques and apparatus for swapping a primary power source (e.g., a main battery) while using a secondary power source (e.g., a backup battery or a supercapacitor) to power a portable device. One example integrated circuit (IC) for power management generally includes a first power supply node; a second power supply node; a first port for coupling to a primary power source; a first switch coupled between the first power supply node and the first port; a second port for coupling to a secondary power source; a second switch coupled between the first power supply node and the second port; and a third switch coupled between the first and second power supply nodes. For certain aspects, the IC also includes a third power supply node, a voltage regulator coupled between the first and third power supply nodes, and a fourth switch coupled between the second and third power supply nodes.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 26, 2024
    Inventors: Vignesh MARIYAPPAN, Anand Kumar KALAIRAJ, Prashanth Kumar KAKKIRENI, Amit DAS
  • Patent number: 12099397
    Abstract: Various embodiments include power management system methods including receiving, at a processor(s), a notification signal triggering the processor(s) to implement power usage mitigation at the processor(s), determining, by the processor(s), a mitigation amount of power rail power by which to mitigate current usage at a power rail based on a use case for the power rail, and implementing power usage mitigation at the processor(s) by the processor(s) sufficient to mitigate power usage at the power rail by the mitigation amount of power rail power. Power usage mitigation may include reducing processor(s) current usage: by a predefined amount; proportional to the amount a power rail current exceeds a power rail current threshold; by the amount of current exceeding a processor current threshold; or by a smallest amount between the amount a power rail current exceeds a power rail current threshold and the processor(s) current exceeds a processor current threshold.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: September 24, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Prashanth Kumar Kakkireni, Matthew Severson, Ravi Jenkal, Gordon Lee, Kevin Bradley Citterelle, Ronald Alton, Anish Muttreja
  • Publication number: 20240211021
    Abstract: Various embodiments include power management system methods including receiving, at a processor(s), a notification signal triggering the processor(s) to implement power usage mitigation at the processor(s), determining, by the processor(s), a mitigation amount of power rail power by which to mitigate current usage at a power rail based on a use case for the power rail, and implementing power usage mitigation at the processor(s) by the processor(s) sufficient to mitigate power usage at the power rail by the mitigation amount of power rail power. Power usage mitigation may include reducing processor(s) current usage: by a predefined amount; proportional to the amount a power rail current exceeds a power rail current threshold; by the amount of current exceeding a processor current threshold; or by a smallest amount between the amount a power rail current exceeds a power rail current threshold and the processor(s) current exceeds a processor current threshold.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 27, 2024
    Inventors: Prashanth Kumar KAKKIRENI, Matthew SEVERSON, Ravi JENKAL, Gordon LEE, Kevin Bradley CITTERELLE, Ronald ALTON, Anish MUTTREJA
  • Patent number: 11733767
    Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: August 22, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Prashanth Kumar Kakkireni, Matthew Severson, Kumar Kanti Ghosh, Shishir Joshi
  • Patent number: 11630694
    Abstract: Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: April 18, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Vijayakumar Ashok Dibbad, Bharat Kumar Rangarajan, Prashanth Kumar Kakkireni, Srinivas Turaga
  • Publication number: 20220413593
    Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Prashanth Kumar KAKKIRENI, Matthew SEVERSON, Kumar Kanti GHOSH, Shishir JOSHI
  • Publication number: 20220222112
    Abstract: Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.
    Type: Application
    Filed: January 13, 2021
    Publication date: July 14, 2022
    Inventors: Vijayakumar Ashok DIBBAD, Bharat Kumar RANGARAJAN, Prashanth Kumar KAKKIRENI, Srinivas TURAGA
  • Patent number: 11366508
    Abstract: Systems, methods, and apparatus for power management are disclosed. A power management integrated circuit has a bus interface circuit configured to couple the power management integrated circuit to a shared communication bus, one or more regulator circuits configured to provide current to a managed device, and a controller. The controller is configured to determine that current consumption by the managed device exceeds a threshold level, generate an extended current level message to be transmitted over the shared communication bus to the managed device and transmit a time value with the extended current level message, the time value indicative of an elapsed time between generation of the extended current level message and start of transmission of the extended current level message.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: June 21, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Prashanth Kumar Kakkireni, Naveen Kumar Narala, Sharon Graif