Abstract: Systems and methods for multi-layer optical proximity correction (OPC) metrology. The OPC metrology system accesses three layers of OPC contour data, the layers of OPC data generated for a drawn integrated circuit layout characterized for a foundry process node. The three layers include a first metal layer, a second metal layer, and a via layer. A feature, such as a via, is formed in the three layers. The system receives user input defining a check (geometric analysis) for the feature, and a limit. The system performs the check on the features and generates a flag for the feature when the limit is exceeded. The system can generate output that reflects the integration of multiple checks and predicts risks and yields for the foundry process node.

Abstract: This disclosure describes systems, methods, and devices related to shifting layouts of electronic circuit vias during optical proximity corrections (OPC). A method may include identifying a first metal line, of an electronic circuit, drawn at a first position; identifying a second metal line, of the electronic circuit, drawn at a second position; identifying a via drawn at a third position extending between the first metal line and the second metal line; determining a fourth position to which the first metal line is to move from the first position; determining a fifth position to which the second metal line is to move from the second position; determining, based on the fourth position, the fifth position, a sixth position to which the via is to move from third position; and generating a layout for generating a photomask for the via at the sixth position.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to adjust vias in integrated circuits (ICs) based on machine learning (ML). An example apparatus computes a dimension by which to extend a via based on at least one of a first metal wire in a first layer of the IC above the via, a via-to-via patterning constraint, or a via-to-metal shorting constraint for a second layer of the IC below the via. The example apparatus also computes a shifted position of the via based on at least one of (a) the dimension or (b) a width and a position of a second metal wire below the via, the width and the position predicted by an ML model. Additionally, the example apparatus adjusts a configuration file corresponding to the IC based on at least one of the dimension or the shifted position of the via.