Patents by Inventor Prashanth Nimmala

Prashanth Nimmala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus, method, and system for instantaneous cache state recovery from speculative abort/commit
    Patent number: 9274962
    Abstract: An apparatus and method is described herein for providing instantaneous, efficient cache state recover upon an end of speculative execution. Speculatively accessed entries of a cache memory are marked as speculative, which may be on a thread specific basis. Upon an end of speculation, the speculatively marked entries are transitioned in parallel by a speculative port to their appropriate, thread specific, non-speculative coherency state; these parallel transitions allow for instantaneous commit or recovery of speculative memory state.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: March 1, 2016
    Assignee: Intel Corporation
    Inventors: Prashanth Nimmala, Hamid-Reza S. Bonakdar
  • Integrating intellectual property (IP) blocks into a processor
    Patent number: 9021156
    Abstract: In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: April 28, 2015
    Inventors: Prashanth Nimmala, Robert J. Greiner, Lily P. Looi, Rupin H. Vakharwala, Marcus W. Song, James A. Beavens, Aimee D. Wood, Jeff V. Tran
  • Integrating Intellectual Property (IP) Blocks Into A Processor
    Publication number: 20130054845
    Abstract: In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Inventors: Prashanth Nimmala, Robert J. Greiner, Lily P. Looi, Rupin H. Vakharwala, Marcus W. Song, James A. Beavens, Aimee D. Wood, Jeff V. Tran
  • APPARATUS, METHOD, AND SYSTEM FOR INSTANTANEOUS CACHE STATE RECOVERY FROM SPECULATIVE ABORT/COMMIT
    Publication number: 20120144126
    Abstract: An apparatus and method is described herein for providing instantaneous, efficient cache state recover upon an end of speculative execution. Speculatively accessed entries of a cache memory are marked as speculative, which may be on a thread specific basis. Upon an end of speculation, the speculatively marked entries are transitioned in parallel by a speculative port to their appropriate, thread specific, non-speculative coherency state; these parallel transitions allow for instantaneous commit or recovery of speculative memory state.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 7, 2012
    Inventors: Prashanth Nimmala, Hamid-Reza S. Bonakdar