Abstract: The independent claims of this patent signify a concise description of embodiments. Each component of a testbench configured to test a DUT is associated at compile time with a different hardware transactor. The testbench is partitioned at compile time into a plurality of independent partitioned testbenches, where each independent partitioned testbench comprises at least one component of the testbench. At run time, each of the plurality of partitioned testbenches is simulated in parallel. The simulating of a partitioned testbench includes execution of its at least one component on its at least one associated hardware transactor using the hardware emulation system. This Abstract is not intended to limit the scope of the claims.

Abstract: The independent claims of this patent signify a concise description of embodiments. Each component of a testbench configured to test a DUT is associated at compile time with a different hardware transactor. The testbench is partitioned at compile time into a plurality of independent partitioned testbenches, where each independent partitioned testbench comprises at least one component of the testbench. At run time, each of the plurality of partitioned testbenches is simulated in parallel. The simulating of a partitioned testbench includes execution of its at least one component on its at least one associated hardware transactor using the hardware emulation system. This Abstract is not intended to limit the scope of the claims.

Abstract: A method and system optimize the time interval for a scheduled synchronization or sync between entities. The optimization of the scheduled sync may be obtained by dynamically varying the sync interval time instead of a fixed preset time interval. The method varies the scheduled sync interval based on the parameters which may include data traffic used in the sync application, a battery level status, a network type, and a roaming status. Using the method, the number of unsuccessful sync requests may be reduced.