Patents by Inventor Prashanth Vallur

Prashanth Vallur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adaptive digital delay line for characterization of clock uncertainties
    Patent number: 9494649
    Abstract: An integrated circuit (IC) measures uncertainties in a first signal. The IC comprises a programmable delay circuit to introduce a programmable delay to the first signal to generate a first delayed signal. The IC further comprises a digital delay line (DDL) comprising a first delay chain of delay elements having input to receive the first delayed signal. The DDL further comprises a set of storage elements, each storage element having an input coupled to an output of a corresponding delay element of the first delay chain, and an output to provide a corresponding bit of a digital reading. The DDL additionally comprises a decoder to generate a digital signature from the digital reading and a controller to iteratively adjust the programmed delay of the programmable delay circuit to search for a failure in a resulting digital signature.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: November 15, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arun S. Iyer, Prashanth Vallur, Shraddha Padiyar, Amit Govil
  • ADAPTIVE DIGITAL DELAY LINE FOR CHARACTERIZATION OF CLOCK UNCERTAINTIES
    Publication number: 20140184243
    Abstract: An integrated circuit (IC) measures uncertainties in a first signal. The IC comprises a programmable delay circuit to introduce a programmable delay to the first signal to generate a first delayed signal. The IC further comprises a digital delay line (DDL) comprising a first delay chain of delay elements having input to receive the first delayed signal. The DDL further comprises a set of storage elements, each storage element having an input coupled to an output of a corresponding delay element of the first delay chain, and an output to provide a corresponding bit of a digital reading. The DDL additionally comprises a decoder to generate a digital signature from the digital reading and a controller to iteratively adjust the programmed delay of the programmable delay circuit to search for a failure in a resulting digital signature.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Arun S. Iyer, Prashanth Vallur, Shraddha Padiyar, Amit Govil