Patents by Inventor Prashantha Kalluraya

Prashantha Kalluraya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bus device that concurrently synchronizes source synchronous data while performing error detection and correction
    Patent number: 7139965
    Abstract: A bus device comprises a clock generator that is adapted to generate a clock signal for internal use by the bus device, data synchronizing logic that is adapted to synchronize source synchronous data that the bus device receives from the bus to the bus device's clock signal, and error detection and correction logic coupled to the data synchronizing logic. The error detection and correction logic is adapted to detect and correct errors associated with the data received from the bus concurrently while the data synchronizing logic synchronizes source synchronous data received from the bus to the clock signal.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: November 21, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paras A. Shah, Prashantha Kalluraya
  • Universal asynchronous boundary module
    Patent number: 6959398
    Abstract: An application specific integrated circuit (ASIC) employs various logic blocks. The blocks may include logic circuits that operate at different clock rates. Consequently, an interface logic block may be needed to efficiently transfer signals from one frequency clock domain to another. One such interface, known as a universal asynchronous boundary module (UABM) is situated between the two domains allowing communication between the logic circuits.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: October 25, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paras A. Shah, Prashantha Kalluraya
  • Bus device that concurrently synchronizes source synchronous data while performing error detection and correction
    Publication number: 20050081129
    Abstract: A bus device comprises a clock generator that is adapted to generate a clock signal for internal use by the bus device, data synchronizing logic that is adapted to synchronize source synchronous data that the bus device receives from the bus to the bus device's clock signal, and error detection and correction logic coupled to the data synchronizing logic. The error detection and correction logic is adapted to detect and correct errors associated with the data received from the bus concurrently while the data synchronizing logic synchronizes source synchronous data received from the bus to the clock signal.
    Type: Application
    Filed: October 8, 2003
    Publication date: April 14, 2005
    Inventors: Paras Shah, Prashantha Kalluraya
  • Universal asynchronous boundary module
    Publication number: 20030126491
    Abstract: An application specific integrated circuit (ASIC) employs various logic blocks. The blocks may include logic circuits that operate at different clock rates. Consequently, an interface logic block may be needed to efficiently transfer signals from one frequency clock domain to another. One such interface, known as a universal asynchronous boundary module (UABM) is situated between the two domains allowing communication between the logic circuits.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 3, 2003
    Inventors: Paras A. Shah, Prashantha Kalluraya