Patents by Inventor Prasoonkumar P. Surti

Prasoonkumar P. Surti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Replacement policies for a hybrid hierarchical cache
    Patent number: 10691617
    Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Joydeep Ray, James A. Valerio, Altug Koker, Prasoonkumar P. Surti, Balaji Vembu, Wenyin Fu, Bhushan M. Borole, Kamal Sinha
  • Dynamic page sizing of page table entries
    Patent number: 10319070
    Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Joydeep Ray, Altug Koker, Balaji Vembu, Prasoonkumar P. Surti, Kamal Sinha, Vasanth Ranganathan, Kiran C. Veernapu, Bhushan M. Borole, Wenyin Fu
  • Dynamic Page Sizing of Page Table Entries
    Publication number: 20190026856
    Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.
    Type: Application
    Filed: September 4, 2018
    Publication date: January 24, 2019
    Inventors: Abhishek R. Appu, Joydeep Ray, Altug Koker, Balaji Vembu, Prasoonkumar P. Surti, Kamal Sinha, Vasanth Ranganathan, Kiran C. Veernapu, Bhushan M. Borole, Wenyin Fu
  • Replacement Policies for a Hybrid Hierarchical Cache
    Publication number: 20190018799
    Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.
    Type: Application
    Filed: August 27, 2018
    Publication date: January 17, 2019
    Inventors: Abhishek R. Appu, Joydeep Ray, James A. Valerio, Altug Koker, Prasoonkumar P. Surti, Balaji Vembu, Wenyin Fu, Bhushan M. Borole, Kamal Sinha
  • Dynamic page sizing of page table entries
    Patent number: 10157444
    Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Joydeep Ray, Altug Koker, Balaji Vembu, Prasoonkumar P. Surti, Kamal Sinha, Vasanth Ranganathan, Kiran C. Veernapu, Bhushan M. Borole, Wenyin Fu
  • Replacement Policies for a Hybrid Hierarchical Cache
    Publication number: 20180300260
    Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 18, 2018
    Inventors: Abhishek R. Appu, Joydeep Ray, James A. Valerio, Altug Koker, Prasoonkumar P. Surti, Balaji Vembu, Wenyin FU, Bhushan M. Borole, Kamal Sinha
  • Replacement policies for a hybrid hierarchical cache
    Patent number: 10102149
    Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Joydeep Ray, James A. Valerio, Altug Koker, Prasoonkumar P. Surti, Balaji Vembu, Wenyin Fu, Bhushan M. Borole, Kamal Sinha
  • Dynamic Page Sizing of Page Table Entries
    Publication number: 20180293702
    Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Abhishek R. Appu, Joydeep Ray, Altug Koker, Balaji Vembu, Prasoonkumar P. Surti, Kamal Sinha, Vasanth Ranganathan, Kiran C. Veernapu, Bhushan M. Borole, Wenyin Fu