Patents by Inventor Prasoonkumar Surti

Prasoonkumar Surti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10573066
    Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh, Joydeep Ray, Abhishek R. Appu
  • Patent number: 10573055
    Abstract: An apparatus and method for programmable depth stencil pipeline stage and shading. For example, one embodiment of a graphics processing apparatus comprises: a rasterizer to generate a plurality of pixel blocks, one or more of which overlap one or more primitives; programmable depth stencil circuitry to perform depth stencil tests on the pixels which overlap the one or more primitives to identify pixels which pass the depth stencil tests; and thread dispatch circuitry to dispatch pixel shader threads to perform pixel shading operations on those pixels which pass the depth stencil tests, the thread dispatch circuitry including thread dispatch recombine logic to combine pixels which have passed the depth stencil test from multiple pixel blocks into a set of pixel shader threads to be executed concurrently on single instruction multiple data (SIMD) hardware.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: John G. Gierach, Darrel K. Palke, Travis T. Schluessler, Prasoonkumar Surti
  • Patent number: 10565676
    Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: February 18, 2020
    Assignee: INTEL CORPORATION
    Inventors: Adam T. Lake, Guei-Yuan Lueh, Balaji Vembu, Murali Ramadoss, Prasoonkumar Surti, Abhishek R. Appu, Altug Koker, Subramaniam M. Maiyuran, Eric C. Samson, David J. Cowperthwaite, Zhi Wang, Kun Tian, David Puffer, Brian T. Lewis
  • Publication number: 20200051309
    Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.
    Type: Application
    Filed: August 9, 2019
    Publication date: February 13, 2020
    Applicant: Intel Corporation
    Inventors: HUGUES LABBE, DARREL PALKE, SHERINE ABDELHAK, JILL BOYCE, VARGHESE GEORGE, SCOTT JANUS, ADAM LAKE, ZHIJUN LEI, ZHENGMIN LI, MIKE MACPHERSON, CARL MARSHALL, SELVAKUMAR PANNEER, PRASOONKUMAR SURTI, KARTHIK VEERAMANI, DEEPAK VEMBAR, VALLABHAJOSYULA SRINIVASA SOMAYAZULU
  • Publication number: 20200050452
    Abstract: Disclosed embodiments relate to apparatuses, systems, and methods for performing sort indexing and/or permutation using an index. An exemplary apparatus includes decode circuitry to decode an instruction, the instruction to include a first field to identify a location of a source vector, a second field to identify a location of a destination vector, and an opcode to indicate to execution circuitry to execute the decoded instruction to sort values of the source vector and store a result of the sort in the destination vector by generating, per each element of the source vector, an index value using one or more comparisons of the element itself and to other data elements of the source vector, and permuting the values of the elements of the source vector based upon the index values for the elements and execution circuitry to execute the decoded instruction as indicated by the opcode.
    Type: Application
    Filed: March 27, 2019
    Publication date: February 13, 2020
    Inventors: Dan BAUM, Ronen ZOHAR, Asit MISHRA, Prasoonkumar Surti, Elmoustapha OULD-AHMED-VALL, Christopher HUGHES, Alexander HEINECKE
  • Patent number: 10558254
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: February 11, 2020
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Altug Koker, Eric J. Hoekstra, Kiran C. Veernapu, Prasoonkumar Surti, Vasanth Ranganathan, Kamal Sinha, Balaji Vembu, Eric J. Asperheim, Sanjeev S. Jahagirdar, Joydeep Ray
  • Publication number: 20200045348
    Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to decode point cloud data, reconstruct the decoded point cloud data and fill one or more holes in reconstructed point cloud frame data using patch metadata included in the decoded point cloud data and a memory communicatively coupled to the one or more processors.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Applicant: Intel Corporation
    Inventors: Jill Boyce, Scott Janus, Prasoonkumar Surti, Stanley Baran, Michael Apodaca, Srikanth Potluri, Hugues Labbe, Jong Dae Oh, Gokcen Cilingir, Archie Sharma, Jeffrey Tripp, Jason Ross, Barnan Das
  • Publication number: 20200045344
    Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to receive point cloud data included in the video bit stream data to be projected into two or more angles and encode multiple projections for a point cloud point upon a determination that the point cloud point will be included in patches in two or more of the multiple projections.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Applicant: Intel Corporation
    Inventors: Jill Boyce, Atsuo Kuwahara, Tzach Ashkenazi, Ilan Beer, Eytan Kats, Prasoonkumar Surti, Kai Xiao, Jeffrey Tripp, Narayan Biswal, Jason Tanner, Nilesh Shah, Yi-Jen Chiu, Mayuresh M. Varerkar, Maria Bortman, Jonathan Distler, Itay Kaufman
  • Publication number: 20200043121
    Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to decode occupancy map data and auxiliary patch information and generate a plurality of patch video frames based on patch data decoded from the occupancy map data and auxiliary patch information, and a memory communicatively coupled to the one or more processors.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Applicant: Intel Corporation
    Inventors: Jill Boyce, Sang-hee Lee, Scott Janus, Stanley Baran, Michael Apodaca, Prasoonkumar Surti, Srikanth Potluri, Atsuo Kuwahara, Kai Xiao, Jason Tanner, Gokcen Cilingir, Archie Sharma, Jeffrey Tripp, Jason Ross, Barnan Das
  • Publication number: 20200043218
    Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 6, 2020
    Inventors: KARTHIK VAIDYANATHAN, WON-JONG LEE, GABOR LIKTOR, JOHN G. GIERACH, PAWEL MAJEWSKI, PRASOONKUMAR SURTI, CARSTEN BENTHIN, Sven WOOP, THOMAS RAOUX
  • Publication number: 20200045285
    Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Applicant: Intel Corporation
    Inventors: MAYURESH VARERKAR, STANLEY BARAN, MICHAEL APODACA, PRASOONKUMAR SURTI, ATSUO KUWAHARA, NARAYAN BISWAL, JILL BOYCE, YI-JEN CHIU, GOKCEN CILINGIR, BARNAN DAS, ATUL DIVEKAR, SRIKANTH POTLURI, NILESH SHAH, ARCHIE SHARMA
  • Publication number: 20200045343
    Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Applicant: Intel Corporation
    Inventors: Jill Boyce, Scott Janus, Itay Kaufman, Archie Sharma, Stanley Baran, Michael Apodaca, Prasoonkumar Surti, Srikanth Potluri, Barnan Das, Hugues Labbe, Jong Dae Oh, Gokcen Cilingir, Maria Bortman, Tzach Ashkenazi, Jonathan Distler, Atul Divekar, Mayuresh M. Varerkar, Narayan Biswal, Nilesh V. Shah, Atsuo Kuwahara, Kai Xiao, Jason Tanner, Jeffrey Tripp
  • Publication number: 20200043224
    Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 6, 2020
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh, Joydeep Ray, Abhishek R. Appu
  • Publication number: 20200034946
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.
    Type: Application
    Filed: August 5, 2019
    Publication date: January 30, 2020
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
  • Patent number: 10546393
    Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: January 28, 2020
    Assignee: INTEL CORPORATION
    Inventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-Ahmed-Vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
  • Publication number: 20200026514
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: July 30, 2019
    Publication date: January 23, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu, Subramaniam Maiyuran, Prasoonkumar Surti, Guei-Yuan Lueh, David Puffer, Supratim Pal, Eric J. Hoekstra, Travis T. Schluessler, Linda L. Hurd
  • Publication number: 20200019401
    Abstract: A mechanism is described for facilitating intelligent dispatching and vectorizing at autonomous machines. A method of embodiments, as described herein, includes detecting a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a graphics processor. The method may further include determining a first set of threads of the plurality of threads that are similar to each other or have adjacent surfaces, and physically clustering the first set of threads close together using a first set of adjacent compute blocks.
    Type: Application
    Filed: June 18, 2019
    Publication date: January 16, 2020
    Applicant: Intel Corporation
    Inventors: Feng Chen, Narayan Srinivasa, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Joydeep Ray, Nicolas C. Galoppo Von Borries, Prasoonkumar Surti, Ben J. Ashbaugh, Sanjeev Jahagirdar, Vasanth Ranganathan
  • Publication number: 20200019844
    Abstract: A mechanism is described for facilitating smart collection of data and smart management of autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and combining a first computation directed to be performed locally at a local computing device with a second computation directed to be performed remotely at a remote computing device in communication with the local computing device over the one or more networks, where the first computation consumes low power, wherein the second computation consumes high power.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 16, 2020
    Applicant: Intel Corporation
    Inventors: Brian T. Lewis, Feng Chen, Jeffrey R. Jackson, Justin E. Gottschlich, Rajkishore Barik, Xiaoming Chen, Prasoonkumar Surti, Mike B. Macpherson, Murali Sundaresan
  • Publication number: 20200013194
    Abstract: An apparatus to facilitate compute compression is disclosed. The apparatus includes a graphics processing unit including mapping logic to map a first block of integer pixel data to a compression block and compression logic to compress the compression block.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 9, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Balaji Vembu, Prasoonkumar Surti, Kamal Sinha, Nadathur Rajagoplan Satish, Narayan Srinivasa, Feng Chen, Dukhwan Kim, Farshad Akhbari
  • Publication number: 20200004548
    Abstract: An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.
    Type: Application
    Filed: July 5, 2019
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Abhishek R. Appu, Joydeep Ray, Subramaniam M. Maiyuran, Altug Koker