Abstract: Methods and systems for designing a high resolution ADC by eliminating the errors in the ADC stages. An error correction architecture and method of the embodiments of the invention eliminate the gain error and settling error of the residue amplifier in a pipelined ADC stage. A reference voltage error correction architecture and method of the embodiments of the invention eliminate the reference voltage error due to the sampling action in the ADC. The gain error correction method calculates the gain error using an error amplifier and eliminates the gain error at a later stage of the ADC. The reference voltage error correction method calculates the reference voltage error using an ideal reference voltage and corrects the error at a later stage of the ADC. The constraints of gain and settling of the residue amplifier is significantly reduced using the embodiments of the invention.