Patents by Inventor Prasun Kali BHATTACHARYYA
Prasun Kali BHATTACHARYYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10666469Abstract: A digital signal processing circuit comprises a first equalizer circuit and a second equalizer circuit. An output of the second equalizer is used as feedback to generate an equalized signal. The output of the second equalizer circuit is based on a plurality of postcursor values and a plurality of precursor values, where the precursor values are generated based on an output of the first DFE circuit, and the postcursor values are generated independently of the output of the first DFE.Type: GrantFiled: April 29, 2019Date of Patent: May 26, 2020Assignee: MaxLinear, Inc.Inventors: Prasun Kali Bhattacharyya, Joseph Palackal Mathew
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Publication number: 20200021250Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may include at least two processing paths, each including at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may include adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.Type: ApplicationFiled: September 26, 2019Publication date: January 16, 2020Inventors: Prasun Kali Bhattacharyya, Abhishek Ghosh, Prasenjit Bhowmik
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Publication number: 20190342129Abstract: A digital signal processing circuit comprises a first equalizer circuit and a second equalizer circuit. An output of the second equalizer is used as feedback to generate an equalized signal. The output of the second equalizer circuit is based on a plurality of postcursor values and a plurality of precursor values, where the precursor values are generated based on an output of the first DFE circuit, and the postcursor values are generated independently of the output of the first DFE.Type: ApplicationFiled: April 29, 2019Publication date: November 7, 2019Inventors: Prasun Kali Bhattacharyya, Joseph Palackal Mathew
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Patent number: 10187017Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.Type: GrantFiled: April 4, 2017Date of Patent: January 22, 2019Assignee: MAXLINEAR, INC.Inventors: Prasun Kali Bhattacharyya, Abhishek Ghosh, Prasenjit Bhowmik
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Publication number: 20180198419Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.Type: ApplicationFiled: April 4, 2017Publication date: July 12, 2018Inventors: Prasun Kali Bhattacharyya, Abhishek Ghosh, Prasenjit Bhowmik
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Publication number: 20160344398Abstract: Systems and methods are provided for cascaded phase-locked loops (PLLs). A plurality of phase-locked loops (PLLs) arranged in a cascaded manner may be used in providing enhanced signal generation. Each PLL generates an output based on a corresponding input and a feedback signal. The input to a first one of plurality of cascaded phase-locked loops (PLLs) comprises an input reference signal; the input to each remaining one of the plurality of the cascaded phase-locked loops (PLLs) corresponds to an output of a preceding one of the plurality of the cascaded phase-locked loops (PLLs); and the output of a last one of the plurality of cascaded phase-locked loops (PLLs) corresponds to an overall output signal of the plurality of cascaded phase-locked loops (PLLs). The frequency of the overall output signal is set based on the one or more adjustments applied in each one of the plurality of cascaded phase-locked loops (PLLs).Type: ApplicationFiled: May 20, 2016Publication date: November 24, 2016Inventors: Prasun Kali Bhattacharyya, Prasenjit Bhowmik, Vamsi Paidi
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Patent number: 8912843Abstract: An ultra low cut-off frequency filter. A filter circuit includes a control circuit responsive to an input signal and a feedback signal to generate a control signal. The filter circuit includes a controllable resistor coupled to the control circuit. The controllable resistor is responsive to a reference signal and the control signal to generate the feedback signal. The filter circuit includes a feedback path coupled to the control circuit and the controllable resistor to couple the feedback signal from the controllable resistor to the control circuit, thereby removing noise from at least one of the input signal and the reference signal, and preventing voltage error in the filter circuit.Type: GrantFiled: January 20, 2011Date of Patent: December 16, 2014Assignee: Cadence AMS Design India Private LimitedInventors: Prasun Kali Bhattacharyya, Sumanth Chakkirala, Prakash Easwaran
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Patent number: 8878510Abstract: A voltage regulator includes an amplifier, a first buffer and a second buffer. The amplifier is designed to generate an error voltage between a reference voltage and a voltage at an output node of the voltage regulator. The first buffer is coupled to receive the amplified error voltage and, in response, to drive a first pass transistor. The first buffer includes a non-linear resistance element. The resistance of the non-linear resistance element varies non-linearly with a load current drawn from the output node. The second buffer is coupled to receive the amplified error voltage, and in response, to drive a second pass transistor. The second buffer includes a linear resistance element. The resistance of the linear element is a constant. The use of the non-linear resistance element enables reduction in power consumption in the voltage regulator.Type: GrantFiled: May 15, 2012Date of Patent: November 4, 2014Assignee: Cadence AMS Design India Private LimitedInventors: Prasun Kali Bhattacharyya, Prakash Easwaran
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Patent number: 8736363Abstract: A circuit for optimizing a power management system. The circuit includes a first amplifier. The first amplifier is responsive to a first reference signal and operable to supply a first load current. The circuit also includes a second amplifier coupled to the first amplifier. The second amplifier is responsive to a second reference signal and operable to supply a second load current. The second load current is lower in magnitude than the first load current, thereby enabling the first amplifier to operate during a first load condition, and the second amplifier to operate during the first load condition and a second load condition. Further, the circuit includes a resistive element coupled to the first amplifier and the second amplifier, to isolate the first amplifier from the second amplifier.Type: GrantFiled: January 20, 2011Date of Patent: May 27, 2014Assignee: Cadence AMS Design India Private LimitedInventors: Prasun Kali Bhattacharyya, Sumanth Chakkirala
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Publication number: 20130307502Abstract: A voltage regulator includes an amplifier, a first buffer and a second buffer. The amplifier is designed to generate an error voltage between a reference voltage and a voltage at an output node of the voltage regulator. The first buffer is coupled to receive the amplified error voltage and, in response, to drive a first pass transistor. The first buffer includes a non-linear resistance element. The resistance of the non-linear resistance element varies non-linearly with a load current drawn from the output node. The second buffer is coupled to receive the amplified error voltage, and in response, to drive a second pass transistor. The second buffer includes a linear resistance element. The resistance of the linear element is a constant. The use of the non-linear resistance element enables reduction in power consumption in the voltage regulator.Type: ApplicationFiled: May 15, 2012Publication date: November 21, 2013Applicant: COSMIC CIRCUITS PVT LTDInventors: Prasun Kali Bhattacharyya, Prakash Easwaran
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Publication number: 20130021092Abstract: An ultra low cut-off frequency filter. A filter circuit includes a control circuit responsive to an input signal and a feedback signal to generate a control signal. The filter circuit includes a controllable resistor coupled to the control circuit. The controllable resistor is responsive to a reference signal and the control signal to generate the feedback signal. The filter circuit includes a feedback path coupled to the control circuit and the controllable resistor to couple the feedback signal from the controllable resistor to the control circuit, thereby removing noise from at least one of the input signal and the reference signal, and preventing voltage error in the filter circuit.Type: ApplicationFiled: January 20, 2011Publication date: January 24, 2013Applicant: Cosmic Circuits Private LimitedInventors: Prasun Kali BHATTACHARYYA, Sumanth Chakkirala, Prakash Easwaran
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Publication number: 20130021094Abstract: A circuit for optimizing a power management system. The circuit includes a first amplifier. The first amplifier is responsive to a first reference signal and operable to supply a first load current. The circuit also includes a second amplifier coupled to the first amplifier. The second amplifier is responsive to a second reference signal and operable to supply a second load current. The second load current is lower in magnitude than the first load current, thereby enabling the first amplifier to operate during a first load condition, and the second amplifier to operate during the first load condition and a second load condition. Further, the circuit includes a resistive element coupled to the first amplifier and the second amplifier, to isolate the first amplifier from the second amplifier.Type: ApplicationFiled: January 20, 2011Publication date: January 24, 2013Applicant: Cosmic Circuits Private LimitedInventors: Prasun Kali BHATTACHARYYA, Sumanth Chakkirala