Patents by Inventor Pratap Narayan Singh
Pratap Narayan Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230324940Abstract: Embodiments of the present disclosure may relate to a voltage reference generator comprising: a local heater structured to generate continuous controlled temperature and uniform thermal profile, at multiple points further comprising a Bipolar Junction, Transistors, and a heating element. Embodiments may additionally include temperature compensated resistances adopted to generate constant temperature compensated voltage reference current using an operational amplifier, a transistor, and two or more resistors, positive and negative. The embodiments may further include, current mirrors comprising a plurality of MOS transistors configured to mirror current flowing in the PMOS transistor.Type: ApplicationFiled: March 29, 2023Publication date: October 12, 2023Applicant: VERVESEMI MICROELECTRONICS PRIVATE LIMITEDInventor: Pratap Narayan SINGH
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Patent number: 11711090Abstract: In accordance with the present invention a system and method for calibration of the current steering DAC is elaborated which helps to reduce design complexity and reduce silicon area required in the design. Present invention is utilising a clocked comparator and plurality of switch transistors 405,305 and AUX DAC in conjunction with digital estimator and digital compensator blocks to estimate the errors in the current sources 406 and compensate the errors using same AUX DAC during normal operation mode.Type: GrantFiled: November 25, 2020Date of Patent: July 25, 2023Assignee: VERVESEMI MICROELECTRONICS PRIVATE LIMITEDInventors: Pratap Narayan Singh, Adeel Ahmad, Chinmaya Dash
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Patent number: 11177822Abstract: The present invention discloses a method of calibrating time interleaved analog to digital converter comprising: sampling a common input signal, said sampling is performed by an array of sub analog to digital converters, each generating individual digital analog equivalent outputs with sampling time errors, said digital outputs are fed to sampling time error estimation circuitry to calculate a digital output proportional to sampling time error between two consecutive channels, without any restriction on input signal or ADC channel design, said timing skew estimator circuitry composed of generating a delayed output of one of the two consecutive ADC channels, channel first and channel second and subtracting the said delayed output with digital output of the said second channel and producing the first subtracted output and output of said second channel subtracted with said first channel output delayed by sampling delay between the two consecutive channels and producing the second subtracted delayed output, absolType: GrantFiled: November 25, 2020Date of Patent: November 16, 2021Assignee: VERVESEMI MICROELECTRONICS PRIVATE LIMITEDInventors: Pratap Narayan Singh, Ashish Kumar Sharma, Chinmaya Dash
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Publication number: 20210159906Abstract: A multilevel analog to digital converter (ADC) is composed of noise shaping filter and multi-level quantizer, where said quantizer is made from an array of comparators, each coupled with one reference level, the said quantizer is coupled with a thermometric digital to analog converters (DAC) in the feedback path, the said DAC output is compared with ADC input and error is fed to noise shaping filter, said reference levels of each quantizer is generated from a digital to analog converter coupled with a digital quantizer reference controller and said digital quantizer reference controller is randomly changing the reference levels in a way that quantizer coupled DAC elements are indirectly randomised to improve the overall linearity and noise performance of the converter.Type: ApplicationFiled: November 25, 2020Publication date: May 27, 2021Applicant: VERVESEMI MICROELECTRONICS PRIVATE LIMITEDInventors: Pratap Narayan SINGH, Rajeev JAIN, Ashish Kumar SHARMA, Chinmaya DASH
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Publication number: 20210159908Abstract: The present invention discloses a method of calibrating time interleaved analog to digital converter comprising: sampling a common input signal, said sampling is performed by an array of sub analog to digital converters, each generating individual digital analog equivalent outputs with sampling time errors, said digital outputs are fed to sampling time error estimation circuitry to calculate a digital output proportional to sampling time error between two consecutive channels, without any restriction on input signal or ADC channel design, said timing skew estimator circuitry composed of generating a delayed output of one of the two consecutive ADC channels, channel first and channel second and subtracting the said delayed output with digital output of the said second channel and producing the first subtracted output and output of said second channel subtracted with said first channel output delayed by sampling delay between the two consecutive channels and producing the second subtracted delayed output, absolType: ApplicationFiled: November 25, 2020Publication date: May 27, 2021Applicant: VERVESEMI MICROELECTRONICS PRIVATE LIMITEDInventors: Pratap Narayan SINGH, Ashish Kumar SHARMA, Chinmaya DASH
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Publication number: 20210159907Abstract: In accordance with the present invention a system and method for calibration of the current steering DAC is elaborated which helps to reduce design complexity and reduce silicon area required in the design. Present invention is utilising a clocked comparator and plurality of switch transistors 405,305 and AUX DAC in conjunction with digital estimator and digital compensator blocks to estimate the errors in the current sources 406 and compensate the errors using same AUX DAC during normal operation mode.Type: ApplicationFiled: November 25, 2020Publication date: May 27, 2021Applicant: VERVESEMI MICROELECTRONICS PRIVATE LIMITEDInventors: Pratap Narayan SINGH, Adeel AHMAD, Chinmaya DASH
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Patent number: 10608637Abstract: A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.Type: GrantFiled: September 7, 2017Date of Patent: March 31, 2020Assignee: STMicroelectronics International N.V.Inventors: Prashant Singh, Pratap Narayan Singh
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Patent number: 10505562Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.Type: GrantFiled: December 20, 2018Date of Patent: December 10, 2019Assignee: STMicroelectronics International N.V.Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
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Patent number: 10295416Abstract: A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor at varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.Type: GrantFiled: October 10, 2016Date of Patent: May 21, 2019Assignee: STMicroelectronics International N.V.Inventors: Pratap Narayan Singh, Nitin Bansal
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Publication number: 20190123759Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.Type: ApplicationFiled: December 20, 2018Publication date: April 25, 2019Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
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Publication number: 20190074835Abstract: A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.Type: ApplicationFiled: September 7, 2017Publication date: March 7, 2019Applicant: STMicroelectronics International N.V.Inventors: Prashant Singh, Pratap Narayan Singh
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Patent number: 10171100Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.Type: GrantFiled: July 10, 2018Date of Patent: January 1, 2019Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
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Patent number: 10148277Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.Type: GrantFiled: May 19, 2017Date of Patent: December 4, 2018Assignee: STMicroelectronics International N.V.Inventors: Pratap Narayan Singh, Vivek Tripathi, Anil Kumar, Rakesh Malik
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Publication number: 20180337685Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.Type: ApplicationFiled: May 19, 2017Publication date: November 22, 2018Applicant: STMicroelectronics International N.V.Inventors: Pratap Narayan Singh, Vivek Tripathi, Anil Kumar, Rakesh Malik
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Publication number: 20180323796Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.Type: ApplicationFiled: July 10, 2018Publication date: November 8, 2018Inventors: Ashish KUMAR, Chandrajit Debnath, Pratap Narayan Singh
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Patent number: 10027343Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.Type: GrantFiled: December 28, 2017Date of Patent: July 17, 2018Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
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Publication number: 20180123609Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.Type: ApplicationFiled: December 28, 2017Publication date: May 3, 2018Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
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Publication number: 20180100774Abstract: A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor a varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.Type: ApplicationFiled: October 10, 2016Publication date: April 12, 2018Applicant: STMicroelectronics International N.V.Inventors: Pratap Narayan Singh, Nitin Bansal
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Patent number: 9866233Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.Type: GrantFiled: June 23, 2017Date of Patent: January 9, 2018Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
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Patent number: 9705520Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.Type: GrantFiled: December 15, 2016Date of Patent: July 11, 2017Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh