Patents by Inventor Pratap Narayan Singh

Pratap Narayan Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210159907
    Abstract: In accordance with the present invention a system and method for calibration of the current steering DAC is elaborated which helps to reduce design complexity and reduce silicon area required in the design. Present invention is utilising a clocked comparator and plurality of switch transistors 405,305 and AUX DAC in conjunction with digital estimator and digital compensator blocks to estimate the errors in the current sources 406 and compensate the errors using same AUX DAC during normal operation mode.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 27, 2021
    Applicant: VERVESEMI MICROELECTRONICS PRIVATE LIMITED
    Inventors: Pratap Narayan SINGH, Adeel AHMAD, Chinmaya DASH
  • Publication number: 20210159908
    Abstract: The present invention discloses a method of calibrating time interleaved analog to digital converter comprising: sampling a common input signal, said sampling is performed by an array of sub analog to digital converters, each generating individual digital analog equivalent outputs with sampling time errors, said digital outputs are fed to sampling time error estimation circuitry to calculate a digital output proportional to sampling time error between two consecutive channels, without any restriction on input signal or ADC channel design, said timing skew estimator circuitry composed of generating a delayed output of one of the two consecutive ADC channels, channel first and channel second and subtracting the said delayed output with digital output of the said second channel and producing the first subtracted output and output of said second channel subtracted with said first channel output delayed by sampling delay between the two consecutive channels and producing the second subtracted delayed output, absol
    Type: Application
    Filed: November 25, 2020
    Publication date: May 27, 2021
    Applicant: VERVESEMI MICROELECTRONICS PRIVATE LIMITED
    Inventors: Pratap Narayan SINGH, Ashish Kumar SHARMA, Chinmaya DASH
  • Publication number: 20210159906
    Abstract: A multilevel analog to digital converter (ADC) is composed of noise shaping filter and multi-level quantizer, where said quantizer is made from an array of comparators, each coupled with one reference level, the said quantizer is coupled with a thermometric digital to analog converters (DAC) in the feedback path, the said DAC output is compared with ADC input and error is fed to noise shaping filter, said reference levels of each quantizer is generated from a digital to analog converter coupled with a digital quantizer reference controller and said digital quantizer reference controller is randomly changing the reference levels in a way that quantizer coupled DAC elements are indirectly randomised to improve the overall linearity and noise performance of the converter.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 27, 2021
    Applicant: VERVESEMI MICROELECTRONICS PRIVATE LIMITED
    Inventors: Pratap Narayan SINGH, Rajeev JAIN, Ashish Kumar SHARMA, Chinmaya DASH
  • Patent number: 10608637
    Abstract: A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: March 31, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Prashant Singh, Pratap Narayan Singh
  • Patent number: 10505562
    Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
  • Patent number: 10295416
    Abstract: A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor at varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: May 21, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Pratap Narayan Singh, Nitin Bansal
  • Publication number: 20190123759
    Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
  • Publication number: 20190074835
    Abstract: A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 7, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Prashant Singh, Pratap Narayan Singh
  • Patent number: 10171100
    Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: January 1, 2019
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
  • Patent number: 10148277
    Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: December 4, 2018
    Assignee: STMicroelectronics International N.V.
    Inventors: Pratap Narayan Singh, Vivek Tripathi, Anil Kumar, Rakesh Malik
  • Publication number: 20180337685
    Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 22, 2018
    Applicant: STMicroelectronics International N.V.
    Inventors: Pratap Narayan Singh, Vivek Tripathi, Anil Kumar, Rakesh Malik
  • Publication number: 20180323796
    Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Inventors: Ashish KUMAR, Chandrajit Debnath, Pratap Narayan Singh
  • Patent number: 10027343
    Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 17, 2018
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
  • Publication number: 20180123609
    Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 3, 2018
    Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
  • Publication number: 20180100774
    Abstract: A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor a varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.
    Type: Application
    Filed: October 10, 2016
    Publication date: April 12, 2018
    Applicant: STMicroelectronics International N.V.
    Inventors: Pratap Narayan Singh, Nitin Bansal
  • Patent number: 9866233
    Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: January 9, 2018
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
  • Patent number: 9705520
    Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: July 11, 2017
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
  • Patent number: 9588538
    Abstract: A reference voltage generation circuit, including a first current source in series with a first bipolar transistor; a second current source in series with a first resistor; a third current source in series with a second bipolar transistor, the third current source being assembled as a current mirror with the first current source; a second resistor between the base of the second bipolar transistor and the junction point between the current source and the first resistor; and a fourth current source in series with a third resistor, the junction point between the fourth current source and the third resistor defining a reference voltage terminal.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: March 7, 2017
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Jean-Pierre Blanc, Pratap Narayan Singh
  • Patent number: 9432008
    Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages, to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: August 30, 2016
    Assignees: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: St├ęphane Le Tual, Pratap Narayan Singh
  • Patent number: 9379728
    Abstract: A digital-to-analog converter has an output. An analog-to-digital converter senses a voltage at the output of the digital-to-analog converter and generates a digital voltage signal. A source mismatch estimator processes the digital voltage signal to output an error signal indicative of current source mismatch within the digital-to-analog converter. An error code generator generates a digital calibration signal from the error signal. The digital calibration signal is converted by a redundancy digital-to-analog converter to an analog compensation signal for application to the output of analog-to-digital converter to nullify effects of the current source mismatch.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 28, 2016
    Assignee: STMicroelectronics International N.V.
    Inventors: Pratap Narayan Singh, Shiva Sharath Babu Kaleru, Ankur Bal, Mohit Singh, Rakesh Malik