Abstract: A processor can scan a portion of a vector to identify first nonzero entries. The processor can scan another portion of the vector to identify second nonzero entries. The processor can scale a portion of a matrix using the first nonzero entries to generate first intermediate elements. The processor can scale another portion of the matrix using the second nonzero entries to generate second intermediate elements. The processor can store the first intermediate elements in a first buffer and store the second intermediate elements in a second buffer. The processor can copy a subset of the first intermediate elements from the first buffer to a memory and copy a subset of the second intermediate elements from the second buffer to the memory. The subsets of first and second intermediate elements can be aggregated to generate an output vector.

Abstract: A processor can scan a portion of a vector to identify first nonzero entries. The processor can scan another portion of the vector to identify second nonzero entries. The processor can scale a portion of a matrix using the first nonzero entries to generate first intermediate elements. The processor can scale another portion of the matrix using the second nonzero entries to generate second intermediate elements. The processor can store the first intermediate elements in a first buffer and store the second intermediate elements in a second buffer. The processor can copy a subset of the first intermediate elements from the first buffer to a memory and copy a subset of the second intermediate elements from the second buffer to the memory. The subsets of first and second intermediate elements can be aggregated to generate an output vector.

Abstract: Methods and systems for multiplying a matrix and a vector are described. In an example, the vector may be partitioned into a plurality of vector partitions. The matrix may be partitioned into a plurality of matrix partitions. A plurality of threads may be scheduled to multiply each matrix partition with corresponding vector partition to determine intermediate elements. Intermediate elements determined by each thread may be stored in a local buffer assigned to the corresponding thread. Intermediate elements may be copied from a particular buffer to a memory in response to the particular buffer being full. Upon completion of the plurality of threads, the intermediate elements copied to the memory may be aggregated to generate an output vector that may be a result of multiplication between the matrix and the vector.

Abstract: Methods and systems for multiplying a matrix and a vector are described. In an example, the vector may be partitioned into a plurality of vector partitions. The matrix may be partitioned into a plurality of matrix partitions. A plurality of threads may be scheduled to multiply each matrix partition with corresponding vector partition to determine intermediate elements. Intermediate elements determined by each thread may be stored in a local buffer assigned to the corresponding thread. Intermediate elements may be copied from a particular buffer to a memory in response to the particular buffer being full. Upon completion of the plurality of threads, the intermediate elements copied to the memory may be aggregated to generate an output vector that may be a result of multiplication between the matrix and the vector.

Abstract: A method and structure for OS event notification, including a central processing unit (CPU) and a memory including instructions for an event notification mechanism for monitoring operating system events in an operating system (OS) being executed by the CPU. The OS includes a kernel having a plurality of kernel subcomponents that provide services to one or more applications executing in the OS in a user mode, using system calls to the kernel. The OS event notification mechanism is capable of monitoring events within the kernel, at a level below the user mode level. The OS event notification mechanism includes Application Program Interfaces (APIs) that are standard for the OS.

Abstract: A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.

Abstract: A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.

Abstract: A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.

Abstract: A method and structure for OS event notification, including a central processing unit (CPU) and a memory including instructions for an event notification mechanism for monitoring operating system events in an operating system (OS) being executed by the CPU. The OS includes a kernel having a plurality of kernel subcomponents that provide services to one or more applications executing in the OS in a user mode, using system calls to the kernel. The OS event notification mechanism is capable of monitoring events within the kernel, at a level below the user mode level. The OS event notification mechanism includes Application Program Interfaces (APIs) that are standard for the OS.

Abstract: A method and structure for notifying operating system events, includes standard filesystem interfaces provided for event consumers to use for one or more of registering for event notifications of a set of events, receiving an event notification when each event occurs, and getting details of events that have occurred.

Abstract: A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.

Abstract: A method and structure for notifying operating system events, includes standard filesystem interfaces provided for event consumers to use for one or more of registering for event notifications of a set of events, receiving an event notification when each event occurs, and getting details of events that have occurred.

Abstract: A method and apparatus for creating a compressed trace for a program, wherein events are compressed separately to provide improved compression and tracing. A sequence of events for a program is selected, and a sequence of values is then determined for each of the selected events occurring during an execution of the program. Each sequence of values is then compressed to generate a compressed sequence of values for each event. These values are then ordered in accordance with information stored in selected events (such as for example, branch events), where the ordered values correspond to the trace.

Abstract: A method of determining and using the optimal page size in the execution of an application wherein the number of virtual to real address caching mechanism misses per unit time is calculated for available page sizes and wherein the optimal page size is determined based on the determined number of mechanism misses. In a more specific aspect of this invention, mechanism misses per unit time are calculated for only those applications which are more likely to consume computer system resources. In yet another more specific aspect of this invention, the mechanism misses for a selected application are determined for each of a number of memory address regions.

Abstract: An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of target addresses representing a history of target addresses for a multi-target branch and logic for reading the memory and identifying a repeated pattern in a plurality of target addresses for a multi-target branch. The information processing system further includes logic for predicting a next target address for the multi-target branch based on the repeated pattern that was identified.

Abstract: A method, system, and program key-controlled object-based memory protection are provided. A processing unit includes an authority check for controlling access by the processing unit to pages of memory according to whether a hardware protection key set currently loaded in an authority mask register allows access to the pages. In particular, each page of memory is assigned a page key number that indexes into the hardware protection key set. The currently loaded hardware protection key set specifies those page key numbers that are currently accessible to the processing unit for the execution context. Each hardware key within the hardware protection key set may be associated with a particular data object or group of data objects. Thus, effectively, the currently loaded hardware protection key set identifies which data objects or groups of data objects are currently accessible.

Abstract: A method, information processing system, and computer readable medium for efficiently distributing a computer system's main memory among applications running in that operating system instance. More specifically, threshold values used by a page replacement algorithm of the virtual memory manager are automatically tuned in response to the load on the memory of a computer system. One such threshold value is the lower threshold of free memory which is changed as a function of the load on the memory. For example, such a load might be represented as the number of threads that were added to a waiting queue during a defined interval of time divided by the number of clock tics in that interval. This representation is known as the thread wait rate. This rate is then compared to a target rate to determine if the lower threshold value should be changed. When the free memory space falls below the lower threshold, a page replacement daemon is used to page out memory to make more memory space available.

Abstract: A method and apparatus for creating a compressed trace for a program, wherein events are compressed separately to provide improved compression and tracing. A sequence of events for a program is selected, and a sequence of values is then determined for each of the selected events occurring during an execution of the program. Each sequence of values is then compressed to generate a compressed sequence of values for each event. These values are then ordered in accordance with information stored in selected events (such as for example, branch events), where the ordered values correspond to the trace.

Abstract: The present invention is a process in which broadcasters can supplement existing multimedia streams such as video and audio with additional multimedia streams in a coordinated and integrated way, allowing users, after reception of the broadcast stream, to select which substream to use, without requiring an upstream channel to communicate this user preference back to the server or any additional bandwidth to broadcast these additional streams.

Abstract: The present invention is a process in which broadcasters can supplement existing multimedia streams such as video and audio with additional multimedia streams in a coordinated and integrated way, allowing users, after reception of the broadcast stream, to select which sub-stream to use, without requiring an upstream channel to communicate this user preference back to the server or any additional bandwidth to broadcast these additional streams.