Patents by Inventor Pratap Prasad

Pratap Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260135697
    Abstract: It is provided a non-transitory computer-readable medium storing instructions that, when executed by one or more processing circuitries of an apparatus, causing the one or more processing circuitries to perform locally on the apparatus a method. The method includes receiving configuration inputs for a target semiconductor device, the configuration inputs comprising a device identifier, one or more safety-critical parameters, and profile-specific operational parameters for one or more semiconductor device configuration profiles. The method further includes generating a first set of configuration data for programming into a non-volatile one-time programmable memory of the target semiconductor device. The method further includes generating a second set of configuration data for a non-volatile rewritable memory of the target semiconductor device.
    Type: Application
    Filed: November 14, 2025
    Publication date: May 14, 2026
    Inventors: Miraben PATEL, Ingrid MURPHY, Kamraan NASIM, Daniel APPERLOO, Avi MORALI, Allen GARDINER, Sreenadh KARETI, Pawan CHHABRA, Anthony GIARDINA, Marian CRETU, Marcus WINSTON, Biju Neerthattil SUDHAKARAN, Sean DARDIS, Pratap PRASAD, Sreeja MENON, Joaquin ROMERA
  • Publication number: 20260104749
    Abstract: Some aspects of the present disclosure relate to a power management apparatus for a memory subsystem of a graphics processing unit, the power management apparatus comprising first interface circuitry for communicating with a system firmware of a host computer hosting the graphics processing unit, second interface circuitry for communicating with one or more components of the memory subsystem of the graphics processing unit, processor circuitry configured to obtain a memory subsystem control input from the system firmware, trigger execution of a sequence of operations in response to the memory subsystem control input, and provide a memory subsystem control output to the system firmware based on a result of the sequence of operations.
    Type: Application
    Filed: December 5, 2025
    Publication date: April 16, 2026
    Inventors: Sreeja MENON, Marcus WINSTON, Pawan CHHABRA, Joaquin ROMERA, Marian CRETU, Vinod INIPODU MURUGAN, Sean DARDIS, Ingrid MURPHY, Kamraan NASIM, Daniel APPERLOO, Miraben PATEL, Pratap PRASAD, Biju Neerthattil SUDHAKARAN
  • Publication number: 20260099413
    Abstract: It is provided an apparatus comprising interface circuitry configured to communicate with one or more memory controllers. The apparatus further comprises machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to receive a request from a management component to initiate collection of telemetry data from one or more memory devices. The machine-readable instructions further include instructions to, in response to the request, send a command to the one or more memory controllers to cause the at least one memory controller to read the telemetry data from one or more memory devices. The machine-readable instructions further include instructions to receive the telemetry data from the at least one memory controller, to stage the telemetry data, and to send an acknowledgement to the management component.
    Type: Application
    Filed: November 28, 2025
    Publication date: April 9, 2026
    Inventors: Miraben PATEL, Sreeja MENON, Marcus WINSTON, Ingrid MURPHY, Marian CRETU, Kamraan NASIM, Pawan CHHABRA, Joaquin ROMERA, Sean DARDIS, Anthony GIARDINA, Biju Neerthattil SUDHAKARAN, Pratap PRASAD
  • Publication number: 20260072784
    Abstract: Provided is an apparatus, a device, a method, a computer program, and a non-transitory, computer-readable medium comprising a program code for a computer system, as well as a computer system. An apparatus (10) for a computer system (100) comprises memory circuitry (11) for storing information identifying at least one defective memory hardware location, and one or more hardware address determination circuitries (12, 13) configured to determine a mapping between a physical memory address and a hardware location address of corresponding memory (101, 102), wherein the one or more hardware address determination circuitries are configured to adapt the mapping at run-time upon obtaining updated information identifying at least one defective memory hardware location.
    Type: Application
    Filed: November 14, 2025
    Publication date: March 12, 2026
    Inventors: Sean DARDIS, Pawan CHHABRA, Miraben PATEL, Ingrid MURPHY, Kamraan NASIM, Marcus WINSTON, Sreeja MENON, Pratap PRASAD, Marian CRETU, Biju Neerthattil SUDHAKARAN, Anthony GIARDINA, Joaquin ROMERA
  • Patent number: 10609722
    Abstract: This disclosure relates to a communication device, comprising: a first communication module configured to communicate data with a first communication partner device according to a first wireless technology; a second communication module configured to communicate data with a second communication partner device according to a second wireless technology; and a scheduling module configured to determine a parameter indicative of a receive data capacity of the first communication partner device based on the data communication with the first communication partner device, and to schedule the data communication with the first communication partner device and the data communication with the second communication partner device based on the parameter.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: March 31, 2020
    Assignee: Intel IP Corporation
    Inventors: Itzik Shahar, Hakan Magnus Eriksson, Oren Shalita, Pratap Prasad
  • Publication number: 20200008217
    Abstract: This disclosure relates to a communication device, comprising: a first communication module configured to communicate data with a first communication partner device according to a first wireless technology; a second communication module configured to communicate data with a second communication partner device according to a second wireless technology; and a scheduling module configured to determine a parameter indicative of a receive data capacity of the first communication partner device based on the data communication with the first communication partner device, and to schedule the data communication with the first communication partner device and the data communication with the second communication partner device based on the parameter.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Itzik Shahar, Hakan Magnus Eriksson, Oren Shalita, Pratap Prasad