Abstract: A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.

Abstract: A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.

Abstract: A method for removing offset in a receiver of an integrated circuit (IC) includes: determining digital codes of differential input voltages of an amplifier in a first receiving lane of the receiver; comparing the digital codes to a digital code corresponding to an optimum common mode voltage (VCM) of the receiver; according to the comparison, determining a bias code for adjusting both the differential input voltages to match the optimum VCM; and inputting the bias code to a bias circuit of the receiver. The first receiving lane of the receiver includes a plurality of amplifiers. The method steps are repeated for each amplifier of the plurality of amplifiers, and then repeated for all receiving lanes of the IC.

Abstract: A receiver device and an eye pattern-based control parameter adjustment method are provided. The receiver device includes a receiving circuit and a control circuit. The control circuit performs an iterative operation to determine an optimized control parameter, and updates current control parameters of the receiving circuit to the optimized control parameter after completing the iterative operation. The receiving circuit processes an input signal according to the current control parameters to generate recovered data. The iterative operation includes: updating the current control parameters of the receiving circuit to candidate control parameters; checking a size relationship between an optimized eye mask and a current eye pattern; and increasing the optimized eye mask according to the current eye pattern when the optimized eye mask does not conflict with the current eye pattern, and updating the optimized control parameters to the candidate control parameters corresponding to the new eye mask.

Abstract: An eye opening monitor device and an operation method thereof are provided. The eye opening monitor device includes a phase interpolator, a first sampling circuit, a second sampling circuit, and a clock centering circuit. The first sampling circuit samples a data signal according to a data clock to generate first sampled data. The second sampling circuit samples the data signal according to a phase interpolation clock to generate second sampled data. The phase interpolator changes a phase of the phase interpolation clock according to a phase interpolation code. The clock centering circuit counts multiple comparison results of the first sampled data and the second sampled data in multiple clock cycles to obtain an error count value for any one of different phase interpolation codes. The clock centering circuit determines the phase interpolation code provided to the phase interpolator based on the error count values corresponding to different phase interpolation codes.

Abstract: A dynamic module and a decision feedback equalizer are provided. The decision feedback equalizer includes two dynamic modules, which have symmetric circuits and connections. The dynamic module includes a first domino circuit, a second domino circuit, and a storage circuit. In response to a first previous decision bit and a second previous decision bit, a first multiplexer output and a second multiplexer output are generated. The dynamic module alternatively operates in an evaluation period and a precharge period, depending on a clock signal. In the evaluation period, the first and the second multiplexer outputs are updated by the first domino circuit and the second domino circuit. In the precharge period, the first and the second multiplexer outputs are held by the storage circuit.

Abstract: A calibration circuit, including a duty cycle correction circuit and a phase correction circuit and associated calibrating method, are provided. Firstly, a first duty cycle adjusted clock and a second duty cycle adjusted clock are generated by the duty cycle correction circuit based on a first input clock and a second input clock, respectively. Then, a first delay adjusted clock and a second delay adjusted clock are generated by the phase correction circuit based on a phase of the first duty cycle adjusted clock, and a detection signal is generated. The detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock. Later, the duty cycle correction circuit and the phase correction circuit are controlled in response to the detection signal.

Abstract: A decision feedback equalizer includes a positive signal line, a negative signal line, a sense amplifier, a feedback driver, a load unit, a differential driver, and a charge pump. The differential driver maintains a difference between the first voltage of the positive signal line and the second voltage of the negative signal line at a last time point of the normal period to be equal to or greater than the reference voltage by adjusting strength of the positive input current corresponding to a positive input signal and strength of the negative input current corresponding to a negative input signal based on a temperature signal. The charge pump provides a positive offset voltage and a negative offset voltage to the positive signal line and the negative signal line, respectively. The positive offset voltage and the negative offset voltage are used to maintain an average voltage of the first voltage and the second voltage at the last time point of the normal period at a first value.

Abstract: A decision feedback equalizer includes a positive signal line, a negative signal line, a sense amplifier, a feedback driver, a load unit, a differential driver, and a charge pump. The differential driver maintains a difference between the first voltage of the positive signal line and the second voltage of the negative signal line at a last time point of the normal period to be equal to or greater than the reference voltage by adjusting strength of the positive input current corresponding to a positive input signal and strength of the negative input current corresponding to a negative input signal based on a temperature signal. The charge pump provides a positive offset voltage and a negative offset voltage to the positive signal line and the negative signal line, respectively. The positive offset voltage and the negative offset voltage are used to maintain an average voltage of the first voltage and the second voltage at the last time point of the normal period at a first value.