Patents by Inventor Prateek Sharma
Prateek Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143515Abstract: A system includes host interface circuitry to interact with a host system and that includes an address translation circuit, which includes request staging queues to buffer the address translation requests, each includes a virtual address and received from a host interface circuit. Pending response queues buffer respective address translation requests that are waiting for an address translation from the host system while maintaining an order as received within the request stage queues. Reordering buffers reorder address translations, which are to be supplied to the host interface circuits, according to the order maintained within the pending response queues, each address translation includes a physical address mapped to the virtual address of a corresponding address translation request. A cache stores multiple of the address translations, associated with the address translation requests, for future access by the host interface circuits.Type: ApplicationFiled: October 10, 2023Publication date: May 2, 2024Inventors: Sumangal Chakrabarty, Prateek Sharma, Raja V. S. Halaharivi, Yoav Weinberg, Di Hsien Ngu
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Patent number: 11962500Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.Type: GrantFiled: August 29, 2022Date of Patent: April 16, 2024Assignee: Micron Technology, Inc.Inventors: Aleksei Vlasov, Prateek Sharma, Yoav Weinberg, Scheheresade Virani, Bridget L. Mallak
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Patent number: 11928558Abstract: A request is received associated with a review. Within first content, a first field of interest and a second field of interest are identified and within second content, a third field of interest and a fourth field of interest are identified. A review is generated that includes a first indication of the first field of interest and a second indication of the second field of interest within the first content, as well as a third indication of the third field of interest and a fourth indication of the fourth field of interest within the second content. The review is transmitted to a device of a reviewer for reviewing the content.Type: GrantFiled: November 29, 2019Date of Patent: March 12, 2024Assignee: Amazon Technologies, Inc.Inventors: Siddharth Vivek Joshi, Anuj Gupta, Mark Chien, Jonathan Thomas Greenlee, Stefano Stefani, Warren Barkley, Jon I. Turow, Sindhu Chejerla, Kriti Bharti, Prateek Sharma
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Publication number: 20240069732Abstract: A system includes a memory device, a first interface port and a second interface port operatively coupled with the memory device, and a processing device, operatively coupled with the memory device, to perform operations including: detecting a triggering event associated with the first interface port; responsive to detecting the triggering event, sending an interrupt message to a firmware component of the memory device; receiving, from the firmware component, a configuration setting based on the interrupt message; and allocating, by the processing device, one or more resources to the first interface port according to the configuration setting.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Inventors: Raja V.S. Halaharivi, Prateek Sharma
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Publication number: 20240069807Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving, from a host system, a memory access command; executing the memory access command; identifying a characteristic associated with the memory access command; identifying a threshold period of time corresponding to the characteristic associated with the memory access command; determining that a period of time associated with the memory access command satisfies the threshold period of time; and responsive to determining that the period of time associated with the memory access command satisfies the threshold period of time, notifying the host system of completion of execution of the memory access command.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Inventors: Raja V.S. Halaharivi, Prateek Sharma, Venkat R. Gaddam
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Publication number: 20240024127Abstract: A method for removing a hip stem from bone comprises drilling a channel through the bone adjacent to the hip stem from a proximal end to a distal end thereof, the channel defining a longitudinal first axis. The method further comprises drilling a hole along a second axis through the bone adjacent to a distal end of the hip stem such that the channel and the hole intersect. The method additionally comprises inserting a first end of a cutting wire through the channel and the hole and cutting an interface between the hip stem and the bone with the cutting wire.Type: ApplicationFiled: July 25, 2023Publication date: January 25, 2024Applicant: Howmedica Osteonics Corp.Inventors: Md Rehan, Philip Harris Frank, Prateek Sharma, Mayur Dhawale, Prabhanjan Nimkar, Venus Vermani, Rahul Soni, Subhash Jangid
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Patent number: 11861512Abstract: A request is received associated with reviewing content. As part of the request, one or more conditions are received and the content is analyzed to identify a first field of interest and a second field of interest. The first field of interest and the second field of interest represent fields of interest associated with the review of the content. At least one of the first field of interest or the second field of interest may not satisfy the one or more conditions and the content, or a portion thereof, may be sent for review.Type: GrantFiled: November 27, 2019Date of Patent: January 2, 2024Assignee: Amazon Technologies, Inc.Inventors: Siddharth Vivek Joshi, Stefano Stefani, Warren Barkley, James Andrew Trenton Lipscomb, Fedor Zhdanov, Anuj Gupta, Prateek Sharma, Pranav Sachdeva, Sindhu Chejerla, Jonathan Thomas Greenlee, Jonathan Hedley, Jon I. Turow, Kriti Bharti
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Patent number: 11836511Abstract: A processing device of a memory sub-system can receive a plurality of commands from a plurality of virtual machines via a host interface and associate each of the plurality of commands with a respective function that represents a respective virtual machine from which each of the plurality of commands was received. The controller of the memory sub-system can also setup a respective definition of a respective quality of service for each respective function regarding consumption of resources of the memory device, wherein the controller comprises arbitration circuitry to handle each of the plurality of commands on a per function basis according to the definition.Type: GrantFiled: May 7, 2020Date of Patent: December 5, 2023Assignee: Micron Technology, Inc.Inventors: Prateek Sharma, Bridget L. Mallak, Kevin R. Duncan
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Patent number: 11734191Abstract: A processing device of a memory sub-system can receive a first address from a host and can provide the first address to a memory management unit (MMU) for translation. The processing device can also receive a second address from the MMU wherein the second address is translated from the first address. The processing device can further access the memory device utilizing the second address.Type: GrantFiled: April 1, 2022Date of Patent: August 22, 2023Assignee: Micron Technology, Inc.Inventor: Prateek Sharma
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Patent number: 11659402Abstract: This disclosure relates to providing a reservation signal for cellular communication in unlicensed spectrum. A cellular base station may perform a listen-before-talk procedure on an unlicensed frequency channel. The cellular base station may transmit a reservation signal on the unlicensed frequency channel after successfully performing the listen-before-talk procedure. The cellular base station may perform carrier sensing on the unlicensed frequency channel at least once during the duration of the reservation signal. The cellular base station may perform cellular communication on the unlicensed frequency channel after ceasing transmitting the reservation signal.Type: GrantFiled: March 11, 2020Date of Patent: May 23, 2023Assignee: Apple Inc.Inventors: Deepankar Bhattacharjee, Prateek Sharma, Farouk Belghoul, Dawei Zhang, Haitong Sun, Wei Zeng, Sreevalsan Vallath
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Publication number: 20220417149Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.Type: ApplicationFiled: August 29, 2022Publication date: December 29, 2022Inventors: Aleksei Vlasov, Prateek Sharma, Yoav Weinberg, Scheheresade Virani, Bridget L. Mallak
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Patent number: 11501210Abstract: A request associated with reviewing content for a field of interest is received. A confidence is determined associated with the content including the field of interest. A machine learning (ML) model determines a first confidence associated with the content includes the field of interest. The field of interest is transmitted for review in instances where the first confidence is less than a confidence threshold. After review, an indication associated with a reviewer reviewing the content and the first confidence associated with the ML model identifying the field of interest is updated to a second confidence.Type: GrantFiled: November 27, 2019Date of Patent: November 15, 2022Assignee: Amazon Technologies, Inc.Inventors: Fedor Zhdanov, Siddharth Vivek Joshi, Prateek Sharma, Alisa V. Shinkorenko, Warren Barkley, Stefano Stefani, Krzysztof Chalupka, Pietro Perona
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Patent number: 11431629Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.Type: GrantFiled: August 12, 2020Date of Patent: August 30, 2022Assignee: Micron Technology, Inc.Inventors: Aleksei Vlasov, Prateek Sharma, Yoav Weinberg, Scheheresade Virani, Bridget L. Mallak
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Publication number: 20220222182Abstract: A processing device of a memory sub-system can receive a first address from a host and can provide the first address to a memory management unit (MMU) for translation. The processing device can also receive a second address from the MMU wherein the second address is translated from the first address. The processing device can further access the memory device utilizing the second address.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Inventor: Prateek Sharma
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Publication number: 20220207351Abstract: According to an aspect, a semiconductor design system includes at least one neural network including a first predictive model and a second predictive model, where the first predictive model is configured to predict a first characteristic of a semiconductor device, and the second predictive model is configured to predict a second characteristic of the semiconductor device. The semiconductor design system includes an optimizer configured to use the neural network to generate a design model based on a set of input parameters, where the design model includes a set of design parameters for the semiconductor device such that the first characteristic and the second characteristic achieve respective threshold conditions.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tirthajyoti SARKAR, Diann M. DOW, Gary Horst LOECHELT, Prateek SHARMA
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Publication number: 20220155590Abstract: A heads up display arrangement for a motor vehicle includes a rotatable mirror positioned to reflect a light field produced by a picture generation unit such that the light field is again reflected by a windshield of the motor vehicle and is then visible to a human driver of the motor vehicle as a virtual image. A stepper motor is coupled to the rotatable mirror and rotates the mirror. A stepper motor driver is coupled to the stepper motor and sets a torque of the stepper motor. A temperature sensor detects a temperature associated with the stepper motor. An electronic processor is communicatively coupled to the temperature sensor and to the stepper motor driver. The electronic processor transmits a signal to the stepper motor driver to set a target torque for the stepper motor. The target torque is dependent upon the detected temperature.Type: ApplicationFiled: November 5, 2021Publication date: May 19, 2022Inventors: EDO OMANOVIC, PATRICK O'CONNELL, PRATEEK SHARMA
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Patent number: 11321238Abstract: A processing device of a memory sub-system can receive a first address from a host and can provide the first address to a memory management unit (MMU) for translation. The processing device can also receive a second address from the MMU wherein the second address is translated from the first address. The processing device can further access the memory device utilizing the second address.Type: GrantFiled: August 11, 2020Date of Patent: May 3, 2022Assignee: Micron Technology, Inc.Inventor: Prateek Sharma
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Publication number: 20220060946Abstract: An apparatus, method and system for receiving an input indicating a mode into which to set a user equipment (UE) and at least one further UE associated with the UE, determining whether a connection circuit switched (CS) connectivity or packet switched (PS) connectivity and when the connection is the CS connectivity, generating a short messaging service (SMS) message that indicates the mode corresponding to the input. Also, receiving connectivity information for a plurality of UEs from a cloud network component, the UEs being associated with one another, the connectivity being CS connectivity or PS connectivity, receiving a response indication corresponding to a response performed on an incoming call by a first one of the UEs, the first UE having a PS connectivity, matching the response indication to a corresponding cause code and transmitting the corresponding cause code to a second one of the UEs having a CS connectivity.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Inventors: Prateek SHARMA, Sanjay K. VERMA, Deepankar BHATTACHARJEE, Sairam T. GUTTA, Sreevalsan VALLATH
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Publication number: 20220050788Abstract: A processing device of a memory sub-system can receive a first address from a host and can provide the first address to a memory management unit (MMU) for translation. The processing device can also receive a second address from the MMU wherein the second address is translated from the first address. The processing device can further access the memory device utilizing the second address.Type: ApplicationFiled: August 11, 2020Publication date: February 17, 2022Inventor: Prateek Sharma
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Publication number: 20220050629Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising attempting a communication of a first completion associated with a first transaction processed by the storage system. The operations further comprise, responsive to failure of the communication of the first completion, storing the first completion in a local memory of the storage system and subsequently attempting a communication of the first completion from the local memory.Type: ApplicationFiled: August 13, 2020Publication date: February 17, 2022Inventors: Aleksei Vlasov, Scheheresade Virani, Yoav Weinberg, Prateek Sharma, Venkat R. Gaddam