Abstract: A method includes buffering, in a descriptor queue, descriptors associated with translation units of an LBA-based, direct memory access (DMA) read command of a host system, each descriptor to be linked with a pointer including a physical destination for data associated with a respective translation unit. The method includes sending address translation requests to an address translation circuit for the pointers of respective translation units and detecting an address translation request miss at a cache of the address translation circuit for a first pointer of a first translation unit linked to a first descriptor of the plurality of descriptors. The method includes causing a translation miss message to be sent to a page request interface (PRI) handler, the translation miss message containing a virtual address of the first pointer and to trigger the PRI handler to send a page miss request to a translation agent of the host system.

Abstract: A method, performed by pointer fetch circuitry, includes buffering, in a pointer buffer of host interface circuitry, pointers associated with chop commands of a logical block address read command residing in a submission queue of a host system. The method includes sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit includes a subset of the pointers. The method includes detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command. The method includes sending a translation miss message to a page request interface (PRI) handler. The translation miss message contains a virtual address of the translation unit and a restart point for the chop command, the translation miss message to trigger the PRI handler to send a page miss request to a translation agent of the host system.

Abstract: A system includes a memory device, a first interface port and a second interface port operatively coupled with the memory device, and a processing device, operatively coupled with the memory device, to perform operations including: receiving, from a firmware component of the memory device, a configuration setting based on an interrupt message associated with the first interface port; identifying an arbitration method for allocating one or more resources to the first interface port in a threshold period of time based on the configuration setting; and allocating, by the processing device, the one or more resources to the first interface port according to the identified arbitration method for the threshold period of time, wherein the one or more resources includes memory access commands.

Abstract: A user equipment (UE) is configured with a carrier aggregation (CA) functionality and UE connected to a network via a base station that serves as a primary serving cell (PCell) providing a primary component carrier (PCC) to the UE. The UE determines a plurality of bands that are supported by the UE for use in the CA functionality, generates an individual band information element (IE) including band information for the bands, determines at least one representative CA combination having an order, the order indicating a total number of component carriers (CCs), the at least one representative CA combination forming a basis to extrapolate a plurality of CA combinations having the order based on the band information, generates a representative CA combination IE including the at least one representative CA combination and transmits the individual band IE and the representative CA combination IE to the base station.

Abstract: A system includes a memory device, a first interface port and a second interface port operatively coupled with the memory device, and a processing device, operatively coupled with the memory device, to perform operations including: detecting a triggering event associated with the first interface port; responsive to detecting the triggering event, sending an interrupt message to a firmware component of the memory device; receiving, from the firmware component, a configuration setting based on the interrupt message; and allocating, by the processing device, one or more resources to the first interface port according to the configuration setting.

Abstract: In some implementations, a memory device may obtain, from a host device, a first one or more commands associated with a first identifier. The memory device may maintain a first counter associated with tracking active commands from the host device. The memory device may detect an event, associated with a command, at a first time. The memory device may switch, based on detecting the event, an active identifier for commands obtained after the first time to a second identifier. The memory device may initiate a second counter associated with tracking active commands that were obtained prior to the first time. The memory device may perform an action associated with a command that is associated with the first identifier. The memory device may update, based on performing the action, the first counter and the second counter based on the at least one command being associated with the first identifier.

Abstract: A user equipment (UE) is configured with a carrier aggregation (CA) functionality and UE connected to a network via a base station that serves as a primary serving cell (PCell) providing a primary component carrier (PCC) to the UE. The UE determines a plurality of bands that are supported by the UE for use in the CA functionality, generates an individual band information element (IE) including band information for the bands, determines at least one representative CA combination having an order, the order indicating a total number of component carriers (CCs), the at least one representative CA combination forming a basis to extrapolate a plurality of CA combinations having the order based on the band information, generates a representative CA combination IE including the at least one representative CA combination and transmits the individual band IE and the representative CA combination IE to the base station.

Abstract: A device includes an address translation circuit of host interface circuitry to handle address translation requests to a host system from a host queue interface circuit. The address translation circuit includes cache to store address translations associated with the address translation requests. The host queue interface circuit, coupled to the address translation circuit, is to: pause command fetch arbitration on a submission queue of the host system that is targeted by an address translation request that missed at the cache; trigger a page request interface (PRI) handler to send a page miss request to a translation agent (TA) of the host, the page miss request including a virtual address of the address translation request; receive a restart message from the PRI handler upon the PRI handler receiving a page miss response from the TA; and restart command arbitration on the submission queue that was paused responsive to the restart message.

Abstract: A memory system includes a memory device and a processing device coupled to the memory device, the processing device is to present a plurality of physical or virtual functions (PFs/VFs) to a host computing system; set, for each of the plurality of PFs/VFs, a value of a credit counter to an initial value associated with a Quality of Service (QoS) parameter of a respective PF/VF; responsive to fetching an original command received from the host computing system associated with a specified PF/VF, decrement the value of the credit counter associated with the specified PF/VF; responsive to receiving a reintroduced command associated with the specified PF/VF after the original command, increment the value of the credit counter; determine whether the value of the credit counter is not higher than a threshold value; and responsive to determining that the value of the credit counter is higher than the threshold value, continue fetching a subsequent command associated with the specified PF/VF.

Abstract: A processing device includes host interface circuitry to interact with a host system and an address translation circuit to handle address translation requests to the host system from host interface circuits. The address translation circuit includes a cache to store address translations associated with the address translation requests for future access by host interface circuits. A page request interface (PRI) handler tracks translation miss messages received from the host interface circuits, each translation miss message including a virtual address of a miss at the cache. The PRI handler removes duplicate translation miss messages having an identical virtual address and creates page miss requests from non-duplicate translation miss messages that are categorized into page request groups, each page request group corresponding to a host interface circuit of the host interface circuits. The PRI handler queues the page request groups to be sent to a translation agent of the host system.

Abstract: A system includes host interface circuitry to interact with a host system and that includes an address translation circuit, which includes request staging queues to buffer the address translation requests, each includes a virtual address and received from a host interface circuit. Pending response queues buffer respective address translation requests that are waiting for an address translation from the host system while maintaining an order as received within the request stage queues. Reordering buffers reorder address translations, which are to be supplied to the host interface circuits, according to the order maintained within the pending response queues, each address translation includes a physical address mapped to the virtual address of a corresponding address translation request. A cache stores multiple of the address translations, associated with the address translation requests, for future access by the host interface circuits.

Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.

Abstract: A request is received associated with a review. Within first content, a first field of interest and a second field of interest are identified and within second content, a third field of interest and a fourth field of interest are identified. A review is generated that includes a first indication of the first field of interest and a second indication of the second field of interest within the first content, as well as a third indication of the third field of interest and a fourth indication of the fourth field of interest within the second content. The review is transmitted to a device of a reviewer for reviewing the content.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving, from a host system, a memory access command; executing the memory access command; identifying a characteristic associated with the memory access command; identifying a threshold period of time corresponding to the characteristic associated with the memory access command; determining that a period of time associated with the memory access command satisfies the threshold period of time; and responsive to determining that the period of time associated with the memory access command satisfies the threshold period of time, notifying the host system of completion of execution of the memory access command.

Abstract: A system includes a memory device, a first interface port and a second interface port operatively coupled with the memory device, and a processing device, operatively coupled with the memory device, to perform operations including: detecting a triggering event associated with the first interface port; responsive to detecting the triggering event, sending an interrupt message to a firmware component of the memory device; receiving, from the firmware component, a configuration setting based on the interrupt message; and allocating, by the processing device, one or more resources to the first interface port according to the configuration setting.

Abstract: A method for removing a hip stem from bone comprises drilling a channel through the bone adjacent to the hip stem from a proximal end to a distal end thereof, the channel defining a longitudinal first axis. The method further comprises drilling a hole along a second axis through the bone adjacent to a distal end of the hip stem such that the channel and the hole intersect. The method additionally comprises inserting a first end of a cutting wire through the channel and the hole and cutting an interface between the hip stem and the bone with the cutting wire.

Abstract: A request is received associated with reviewing content. As part of the request, one or more conditions are received and the content is analyzed to identify a first field of interest and a second field of interest. The first field of interest and the second field of interest represent fields of interest associated with the review of the content. At least one of the first field of interest or the second field of interest may not satisfy the one or more conditions and the content, or a portion thereof, may be sent for review.

Abstract: A processing device of a memory sub-system can receive a plurality of commands from a plurality of virtual machines via a host interface and associate each of the plurality of commands with a respective function that represents a respective virtual machine from which each of the plurality of commands was received. The controller of the memory sub-system can also setup a respective definition of a respective quality of service for each respective function regarding consumption of resources of the memory device, wherein the controller comprises arbitration circuitry to handle each of the plurality of commands on a per function basis according to the definition.

Abstract: A processing device of a memory sub-system can receive a first address from a host and can provide the first address to a memory management unit (MMU) for translation. The processing device can also receive a second address from the MMU wherein the second address is translated from the first address. The processing device can further access the memory device utilizing the second address.

Abstract: This disclosure relates to providing a reservation signal for cellular communication in unlicensed spectrum. A cellular base station may perform a listen-before-talk procedure on an unlicensed frequency channel. The cellular base station may transmit a reservation signal on the unlicensed frequency channel after successfully performing the listen-before-talk procedure. The cellular base station may perform carrier sensing on the unlicensed frequency channel at least once during the duration of the reservation signal. The cellular base station may perform cellular communication on the unlicensed frequency channel after ceasing transmitting the reservation signal.