Abstract: According to the present invention, a method and system for emulating multiple electronic designs on a single testbench is disclosed wherein number of instances of the original design to be connected on a single testbench is derived by calculating the capacity of the design and the testbench. It further creates a new wrapper design corresponding to number of instances of the original design; and selectively adapt the design for emulation.

Abstract: The present invention relates to a method to improve the runtime performance of designs with multiple clocks on FPGA's and emulation system. In the method, the compile frequency (FMax) for complex design is improved by breaking-up the critical timing path of the design by inserting pipeline flops iteratively which are clocked at faster available clock frequencies. The method is easily implemented in a design where the clocks are of different frequencies but derived from the same primary clock i.e. the clocks are synchronous to each other and ratio of highest to lowest clock frequencies is more than or equal to 2. It enables optimal usage of emulator up time and hardware area.

Abstract: The present invention provides a method to improve the JTAG debugger connection performance (TCK speed) with CPU for multi-clock designs running on Emulation or FPGA systems by creating two separate emulation or FPGA builds i.e. first build with actual frequency plan and second one with flat frequency plan (all clocks running at same frequency). The method is even effective for enabling JTAG connection to CPU in cases of designs where the running frequency of CPU is so low (due to complex clocking structure like uneven clock frequency ratios and critical paths of the design) that JTAG connection is not possible at all.

Abstract: The present invention provides a method to improve the run time of a SoC design on FPGA and emulation system. A design with multiple clocks is divided or split into multiple smaller designs and is then coupled by synchronizer circuit. The method is particularly more effective in a design where the ratio of highest to lowest clock frequency is high or where clock frequencies are not in even ratios.

Abstract: According to the present invention, a method and system for emulating multiple electronic designs on a single testbench is disclosed wherein number of instances of the original design to be connected on a single testbench is derived by calculating the capacity of the design and the testbench. It further creates a new wrapper design corresponding to number of instances of the original design; and selectively adapt the design for emulation.

Abstract: The present disclosure provides an emulator mapping process on a system-on-a-chip (SoC) for debugging. The implementation reduces manual intervention and makes the emulation mapping process very generic and technology independent and hence it reduces overall project cycle time. In the present disclosure, the SoCs containing analog delay locked loops are made suitable for emulation by configuring analog delay locked loop module in parallel with a synthesizable delay logic module. Further, selection logic is provided to select any one of the module at a time.

Abstract: The present disclosure provides an emulator mapping process on a system-on-a-chip (SoC) for debugging. The implementation reduces manual intervention and makes the emulation mapping process very generic and technology independent and hence it reduces overall project cycle time. In the present disclosure, the SoCs containing analog delay locked loops are made suitable for emulation by configuring analog delay locked loop module in parallel with a synthesizable delay logic module. Further, selection logic is provided to select any one of the module at a time.