Patents by Inventor Prathamesh Amritkar

Prathamesh Amritkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230401124
    Abstract: Media scans to test the integrity of data stored in non-volatile storage are weighted to improve the efficiency of the scans and preserve operating bandwidth of the corresponding device.
    Type: Application
    Filed: August 14, 2023
    Publication date: December 14, 2023
    Inventors: Peng Xu, Fei Liu, Kyoungryun Bae, Jinhyuk Kim, Hyungjin Im, Kyung Ho Kim, Prathamesh Amritkar, Chaohong Hu, Ken Hu
  • Publication number: 20230229358
    Abstract: A zoned namespace (ZNS) storage computing device includes a processor, and non-volatile memory comprising a plurality of zones including a given zone. The processor is configured to execute a zone writing program to receive zone write commands, and responsive to receiving the zone write commands, execute the zone write commands on the given zone of the non-volatile memory of the storage computing device in an order specified by zone write sequence numbers included in a zone descriptor for the given zone.
    Type: Application
    Filed: March 23, 2023
    Publication date: July 20, 2023
    Inventors: Peng Xu, Fei Liu, Kyoungryun Bae, Hyungjin Im, Jinhyuk Kim, Kyung Ho Kim, Prathamesh Amritkar, Chaohong Hu
  • Patent number: 10564895
    Abstract: An infrastructure, method and controller card for managing flash memory in a storage infrastructure. A system is provided that includes flash memory; and a controller that includes: an I/O request handler for handling standard read and write (R/W) operations requested from a host; a garbage collection (GC) system that performs a GC process on the flash memory in response to a threshold condition, wherein the GC process includes GC-induced R/W operations; and a scheduler that interleaves standard R/W operations with GC-induced R/W operations, wherein the scheduler calculates minimum and maximum boundaries for GC-induced R/W operations for a GC process based on an estimated GC latency.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 18, 2020
    Assignee: SCALEFLUX, INC.
    Inventors: Qi Wu, Duy Nguyen, Prathamesh Amritkar, Qing Li
  • Publication number: 20180357011
    Abstract: An infrastructure, method and controller card for managing flash memory in a storage infrastructure. A system is provided that includes flash memory; and a controller that includes: an I/O request handler for handling standard read and write (R/W) operations requested from a host; a garbage collection (GC) system that performs a GC process on the flash memory in response to a threshold condition, wherein the GC process includes GC-induced R/W operations; and a scheduler that interleaves standard R/W operations with GC-induced R/W operations, wherein the scheduler calculates minimum and maximum boundaries for GC-induced R/W operations for a GC process based on an estimated GC latency.
    Type: Application
    Filed: May 11, 2018
    Publication date: December 13, 2018
    Inventors: Qi Wu, Duy Nguyen, Prathamesh Amritkar, Qing Li