Patents by Inventor Prathamesh Chandrashekhar JOSHI

Prathamesh Chandrashekhar JOSHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Lightweight unified power format implementation for emulation and prototyping
    Patent number: 11868696
    Abstract: A method for designing a circuit includes adding, to a circuit design, a power switch configured to produce only one output over an acknowledgement port. The power switch does not include input and output supply ports. The method also includes adding, to the circuit design, an isolation circuit in which only one select pin is used to produce an output. The isolation circuit does not include isolation power and retention circuitry. The method also includes adding, to the circuit design, a retention circuit. The retention circuit includes a clock gating enabled register, a first AND gate connected to a clear pin of the register, and a second AND gate connected to a chip enable pin of the register. The method further includes compiling, by a processing device, the circuit design.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: January 9, 2024
    Assignee: Synopsys, Inc.
    Inventors: Swarup Kumar Pattanayak, Prathamesh Chandrashekhar Joshi
  • LIGHTWEIGHT UNIFIED POWER FORMAT IMPLEMENTATION FOR EMULATION AND PROTOTYPING
    Publication number: 20220207225
    Abstract: A method for designing a circuit includes adding, to a circuit design, a power switch configured to produce only one output over an acknowledgement port. The power switch does not include input and output supply ports. The method also includes adding, to the circuit design, an isolation circuit in which only one select pin is used to produce an output. The isolation circuit does not include isolation power and retention circuitry. The method also includes adding, to the circuit design, a retention circuit. The retention circuit includes a clock gating enabled register, a first AND gate connected to a clear pin of the register, and a second AND gate connected to a chip enable pin of the register. The method further includes compiling, by a processing device, the circuit design.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 30, 2022
    Inventors: Swarup Kumar PATTANAYAK, Prathamesh Chandrashekhar JOSHI