Abstract: A system root of trust device of a computing system authenticates boot images associated with data processing units of the computing system. The device includes at least one processor configured to determine whether a first set of boot code associated with a first processor of the computing system is authentic, in response to determining that the first set of boot code is authentic, reset the first processor to allow the first processor to boot and authenticate first executable code to be executed by the first processor, after resetting the first processor, determine whether a second set of boot code associated with a second processor of the computing system is authentic, and in response to determining that the second set of boot code is authentic, reset the second processor to allow the second processor to boot and to authenticate second executable code to be executed by the second processor.

Abstract: In one example, a data processing unit (DPU) includes a host unit interface for communicatively coupling to second device via a serial input/output (I/O) connection, and a control unit implemented in circuitry and configured to initially configure the host unit interface of a data processing unit to operate in endpoint mode, determine that the host unit interface of the data processing unit is to switch from operating in the endpoint mode to root complex mode, in response to determining that the host unit interface is to switch from operating in the endpoint mode to the root complex mode: configure the host unit interface to operate in the root complex mode, and send data to an I/O expander unit to cause the I/O expander unit to issue a reset signal to the second device, the second device being configured to operate in the endpoint mode.

Abstract: A system root of trust device of a computing system authenticates boot images associated with data processing units of the computing system. The device includes at least one processor configured to determine whether a first set of boot code associated with a first processor of the computing system is authentic, in response to determining that the first set of boot code is authentic, reset the first processor to allow the first processor to boot and authenticate first executable code to be executed by the first processor, after resetting the first processor, determine whether a second set of boot code associated with a second processor of the computing system is authentic, and in response to determining that the second set of boot code is authentic, reset the second processor to allow the second processor to boot and to authenticate second executable code to be executed by the second processor.

Abstract: In one example, a data processing unit (DPU) includes a host unit interface for communicatively coupling to second device via a serial input/output (I/O) connection, and a control unit implemented in circuitry and configured to initially configure the host unit interface of a data processing unit to operate in endpoint mode, determine that the host unit interface of the data processing unit is to switch from operating in the endpoint mode to root complex mode, in response to determining that the host unit interface is to switch from operating in the endpoint mode to the root complex mode: configure the host unit interface to operate in the root complex mode, and send data to an I/O expander unit to cause the I/O expander unit to issue a reset signal to the second device, the second device being configured to operate in the endpoint mode.

Abstract: Techniques are disclosed for an Input/Output (I/O) expansion device configured for slidable insertion within and removal from a plurality of slots of a storage rack having an electrical backplane comprising a plurality of high-speed Peripheral Component Interconnect Express (PCIe) lanes. The I/O expansion device operates as a multi-slot front caddy that extends an I/O interface of the storage rack to allow interconnection with storage and/or compute equipment external from the rack. The I/O expansion device comprises a front plate comprising an aggregate electrical storage connector configured to interface with storage and computing devices. The I/O expansion device comprises a rear plate comprising backplane electrical connectors configured to interface with the high-speed PCIe lanes of the electrical backplane.