Patents by Inventor Prathap SRINIVASAN

Prathap SRINIVASAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INFRASTRUCTURE INTEGRITY CHECKING
    Publication number: 20220382627
    Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 1, 2022
    Inventors: Desmond Fernandes, Indu Prathapan, Jasbir Singh, Prathap Srinivasan, Rishav Karki
  • Infrastructure integrity checking
    Patent number: 11366715
    Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Desmond Fernandes, Indu Prathapan, Jasbir Singh, Prathap Srinivasan, Rishav Karki
  • INFRASTRUCTURE INTEGRITY CHECKING
    Publication number: 20220091928
    Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.
    Type: Application
    Filed: September 22, 2020
    Publication date: March 24, 2022
    Inventors: Desmond FERNANDES, Indu PRATHAPAN, Jasbir SINGH, Prathap SRINIVASAN, Rishav KARKI