Abstract: Herein described are at least a standard cell that is less prone to the negative effects of dynamic IR power supply voltage drops and a method of implementing the standard cell. The standard cell incorporates at least one on-cell capacitor positioned between a power supply rail and a ground rail. The at least one one-cell capacitor provides a charge reservoir for the standard cell to mitigate such dynamic IR power supply voltage drops. The method for implementing the standard cell comprises connecting at least one capacitor across a power supply rail to a ground rail of said standard cell. The at least one capacitor may be implemented by way of using a polysilicon layer and an N-well layer or by way of using a metal layer and an N-well layer.

Abstract: Herein described are at least a layout of an integrated circuit chip that is resistant to the negative effects of IR power supply voltage drops and a method of implementing the integrated circuit chip. The integrated circuit chip layout comprises one or more capacitors positioned in between adjacent functional blocks. The one or more capacitors provide a charge reservoir for use by functional blocks that are affected by IR power supply voltage drops. The method for implementing the integrated circuit chip comprises positioning one or more capacitors in between adjacent functional blocks and connecting one end of each of the one or more capacitors to a power supply rail while connecting the other end to a ground rail. Each of the one or more capacitors may be implemented using a polysilicon layer and an N-well layer.