Patents by Inventor Pratheesh Gangadhar Thalakkal Kottilaveedu
Pratheesh Gangadhar Thalakkal Kottilaveedu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230385107Abstract: A computing resource allocation method comprises beginning a first performance of a first task; determining, using a task manager circuit during the first performance of the first task, that a first operation from among the first plurality of operations requires a resource, wherein the resource is external to the processor; determining, using a spinlock circuit, that the resource is unavailable for use; pausing, under control of the task manager, the first performance of the first task at the processor; beginning, using the processor, a second performance of a second task, the second task comprising a second plurality of operations; receiving, at the task manager, a notice from the spinlock that the resource is currently available for use by the processor; and resuming, under control of the task manager, the first performance of the first task at the processor starting with the first operation from among the first plurality of operations.Type: ApplicationFiled: August 14, 2023Publication date: November 30, 2023Inventors: Anjandeep Singh SAHNI, Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU, William Cronin WALLACE
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Patent number: 11726814Abstract: A computing resource allocation method comprises beginning a first performance of a first task; determining, using a task manager circuit during the first performance of the first task, that a first operation from among the first plurality of operations requires a resource, wherein the resource is external to the processor; determining, using a spinlock circuit, that the resource is unavailable for use; pausing, under control of the task manager, the first performance of the first task at the processor; beginning, using the processor, a second performance of a second task, the second task comprising a second plurality of operations; receiving, at the task manager, a notice from the spinlock that the resource is currently available for use by the processor; and resuming, under control of the task manager, the first performance of the first task at the processor starting with the first operation from among the first plurality of operations.Type: GrantFiled: May 29, 2019Date of Patent: August 15, 2023Assignee: Texas Instruments IncorporatedInventors: Anjandeep Singh Sahni, Pratheesh Gangadhar Thalakkal Kottilaveedu, William Cronin Wallace
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Patent number: 11704154Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.Type: GrantFiled: June 28, 2021Date of Patent: July 18, 2023Assignee: Texas Instruments IncorporatedInventors: Thomas Anton Leyrer, William Cronin Wallace, Pratheesh Gangadhar Thalakkal Kottilaveedu, David Alston Lide
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Patent number: 11579877Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.Type: GrantFiled: April 6, 2021Date of Patent: February 14, 2023Assignee: Texas Instruments IncorporatedInventors: Thomas Anton Leyrer, William Cronin Wallace, David Alston Lide, Pratheesh Gangadhar Thalakkal Kottilaveedu
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Publication number: 20220286412Abstract: An ultra-high speed electronic communications device includes: a network communications interface; a memory; and one or more processing units, communicatively coupled to the memory and the network communications interface, wherein the memory stores instructions configured to cause the one or more processing units to: receive a data packet using the network communications interface; determine a classification of the data packet based, at least in part, on a plurality of factors, wherein the plurality of factors comprises a rate at which the data packet was received and a time at which the data packet was received; select, based at least in part, on the classification, an operation from a plurality of operations, wherein the plurality of operations comprises a cut-through operation and a store-and-forward operation; and perform the selected operation.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Inventors: Thomas Anton LEYRER, William Cronin WALLACE, Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU
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Patent number: 11343205Abstract: An ultra-high speed electronic communications device includes: a network communications interface; a memory; and one or more processing units, communicatively coupled to the memory and the network communications interface, wherein the memory stores instructions configured to cause the one or more processing units to: receive a data packet using the network communications interface; determine a classification of the data packet based, at least in part, on a plurality of factors, wherein the plurality of factors comprises a rate at which the data packet was received and a time at which the data packet was received; select, based at least in part, on the classification, an operation from a plurality of operations, wherein the plurality of operations comprises a cut-through operation and a store-and-forward operation; and perform the selected operation.Type: GrantFiled: May 29, 2019Date of Patent: May 24, 2022Assignee: Texas Instruments IncorporatedInventors: Thomas Anton Leyrer, William Cronin Wallace, Pratheesh Gangadhar Thalakkal Kottilaveedu
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Publication number: 20210326178Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.Type: ApplicationFiled: June 28, 2021Publication date: October 21, 2021Inventors: Thomas Anton LEYRER, William Cronin WALLACE, Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU, David Alston LIDE
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Publication number: 20210224070Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.Type: ApplicationFiled: April 6, 2021Publication date: July 22, 2021Inventors: Thomas Anton LEYRER, William Cronin WALLACE, David Alston LIDE, Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU
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Patent number: 11048552Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.Type: GrantFiled: May 29, 2019Date of Patent: June 29, 2021Assignee: Texas Instruments IncorporatedInventors: Thomas Anton Leyrer, William Cronin Wallace, Pratheesh Gangadhar Thalakkal Kottilaveedu, David Alston Lide
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Publication number: 20190370207Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.Type: ApplicationFiled: May 29, 2019Publication date: December 5, 2019Inventors: Thomas Anton LEYRER, William Cronin WALLACE, Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU, David Alston LIDE
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Publication number: 20190372913Abstract: An ultra-high speed electronic communications device includes: a network communications interface; a memory; and one or more processing units, communicatively coupled to the memory and the network communications interface, wherein the memory stores instructions configured to cause the one or more processing units to: receive a data packet using the network communications interface; determine a classification of the data packet based, at least in part, on a plurality of factors, wherein the plurality of factors comprises a rate at which the data packet was received and a time at which the data packet was received; select, based at least in part, on the classification, an operation from a plurality of operations, wherein the plurality of operations comprises a cut-through operation and a store-and-forward operation; and perform the selected operation.Type: ApplicationFiled: May 29, 2019Publication date: December 5, 2019Inventors: Thomas Anton LEYRER, William Cronin WALLACE, Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU
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Publication number: 20190370063Abstract: A computing resource allocation method comprises beginning a first performance of a first task; determining, using a task manager circuit during the first performance of the first task, that a first operation from among the first plurality of operations requires a resource, wherein the resource is external to the processor; determining, using a spinlock circuit, that the resource is unavailable for use; pausing, under control of the task manager, the first performance of the first task at the processor; beginning, using the processor, a second performance of a second task, the second task comprising a second plurality of operations; receiving, at the task manager, a notice from the spinlock that the resource is currently available for use by the processor; and resuming, under control of the task manager, the first performance of the first task at the processor starting with the first operation from among the first plurality of operations.Type: ApplicationFiled: May 29, 2019Publication date: December 5, 2019Inventors: Anjandeep Singh SAHNI, Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU, William Cronin WALLACE
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Publication number: 20190369996Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.Type: ApplicationFiled: May 29, 2019Publication date: December 5, 2019Inventors: Thomas Anton LEYRER, William Cronin WALLACE, David Alston LIDE, Pratheesh Gangadhar Thalakkal Kottilaveedu
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Patent number: 9153295Abstract: Scratch pad register banks are used as shared fast access storage between processors in a multi processor system. Instead of the usual one to one register mapping between the processors and the scratch pad register banks, an any to any mapping is implemented. The utilization of the scratch pad register banks is improved as the any to any mapping of the registers allow the storage of any processor register anywhere in the scratch pad register bank.Type: GrantFiled: October 4, 2013Date of Patent: October 6, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Pratheesh Gangadhar Thalakkal Kottilaveedu, William C Wallace
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Patent number: 9047188Abstract: In the L2 FIFO architecture incoming frames are stored in a multi bank FIFO to enable offloading the programmable real-time unit to do other tasks. The L2 FIFO buffers data coming from the L1 FIFO, reducing the polling time for received data. Status is always checked for errors before processing the data and updating the state variables. Implementing a state machine to perform some of the checks results in a PRU utilization that is not a function of the bytes that need to be processed.Type: GrantFiled: October 4, 2013Date of Patent: June 2, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Pratheesh Gangadhar Thalakkal Kottilaveedu, Kanad D. Kanhere
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Publication number: 20140101496Abstract: In the L2 FIFO architecture incoming frames are stored in a multi bank FIFO to enable offloading the programmable real-time unit to do other tasks. The L2 FIFO buffers data coming from the L1 FIFO, reducing the polling time for received data. Status is always checked for errors before processing the data and updating the state variables. Implementing a state machine to perform some of the checks results in a PRU utilization that is not a function of the bytes that need to be processed.Type: ApplicationFiled: October 4, 2013Publication date: April 10, 2014Applicant: Texas Instruments IncorporatedInventors: Pratheesh Gangadhar Thalakkal Kottilaveedu, Kanad D. Kanhere
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Publication number: 20140101383Abstract: Scratch pad register banks are used as shared fast access storage between processors in a multi processor system. Instead of the usual one to one register mapping between the processors and the scratch pad register banks, an any to any mapping is implemented. The utilization of the scratch pad register banks is improved as the any to any mapping of the registers allow the storage of any processor register anywhere in the scratch pad register bank.Type: ApplicationFiled: October 4, 2013Publication date: April 10, 2014Applicant: Texas Instruments IncorporatedInventors: Pratheesh Gangadhar Thalakkal Kottilaveedu, William C. Wallace