Patents by Inventor Pratik Marolia
Pratik Marolia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954062Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.Type: GrantFiled: March 14, 2020Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Joydeep Ray, Niranjan Cooray, Subramaniam Maiyuran, Altug Koker, Prasoonkumar Surti, Varghese George, Valentin Andrei, Abhishek Appu, Guadalupe Garcia, Pattabhiraman K, Sungye Kim, Sanjay Kumar, Pratik Marolia, Elmoustapha Ould-Ahmed-Vall, Vasanth Ranganathan, William Sadler, Lakshminarayanan Striramassarma
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Publication number: 20230145856Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.Type: ApplicationFiled: November 30, 2022Publication date: May 11, 2023Applicant: INTEL CORPORATIONInventors: JOSHUA FENDER, UTKARSH Y. KAKAIYA, MOHAN NAIR, BRAIN MORRIS, PRATIK MAROLIA
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Patent number: 11379236Abstract: An apparatus and method for hybrid software-hardware coherency.Type: GrantFiled: December 27, 2019Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Pratik Marolia, Rajesh Sankaran
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Publication number: 20220066931Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.Type: ApplicationFiled: March 14, 2020Publication date: March 3, 2022Applicant: INTEL CORPORATIONInventors: JOYDEEP RAY, NIRANJAN COORAY, SUBRAMANIAM MAIYURAN, ALTUG KOKER, PRASOONKUMAR SURTI, VARGHESE GEORGE, VALENTIN ANDREI, ABHISHEK APPU, GUADALUPE GARCIA, PATTABHIRAMAN K, SUNGYE KIM, SANJAY KUMAR, PRATIK MAROLIA, ELMOUSTAPHA OULD-AHMED-VALL, VASANTH RANGANATHAN, WILLIAM SADLER, LAKSHMINARAYANAN STRIRAMASSARMA
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Patent number: 11201838Abstract: In one embodiment, an input/output port includes a stateful transmit port having: a history storage to store a value corresponding to a transmit on change field of a prior data packet; a comparator to compare a transmit on change field of the data packet to the value stored in the history storage; and a selection circuit to output the data packet without the transmit on change field when the transmit on change field of the data packet matches the value. Other embodiments are described and claimed.Type: GrantFiled: September 25, 2019Date of Patent: December 14, 2021Assignee: Intel CorporationInventors: Pratik Marolia, Rajesh Sankaran, Ishwar Agarwal, Nitish Paliwal
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Publication number: 20210200545Abstract: An apparatus and method for hybrid software-hardware coherency.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Inventors: Pratik Marolia, Rajesh Sankaran
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Publication number: 20210042254Abstract: Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.Type: ApplicationFiled: October 28, 2020Publication date: February 11, 2021Inventors: Pratik Marolia, Andrew Herdrich, Rajesh Sankaran, Rahul Pal, David Puffer, Sayantan Sur, Ajaya Durg
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Publication number: 20210004338Abstract: Methods and apparatus for PASID-based routing extension for Scalable IOV systems. The system may include a Central Processing Unit (CPU) operatively coupled to a scalable Input/Output Virtualization (IOV) device via an in-line device such as a smart controller or accelerator. A Control Process Address Space Identifier (C-PASID) associated with a first memory space is implemented in an Assignable Device Interface (ADI) for the IOV device. The ADI also implements a Data PASID (D-PASID) associated with a second memory space in which data are stored. The C-PASID is used to fetch a descriptor in the first memory space and the D-PASID is employed to fetch data in the second memory space. A hub embedded on the in-line device or implemented as a discrete device is used to steer memory access requests and/or fetches to the CPU or to the in-line device using the C-PASID and D-PASID.Type: ApplicationFiled: September 21, 2020Publication date: January 7, 2021Inventors: Pratik Marolia, Sanjay Kumar, Rajesh Sankaran, Utkarsh Y. Kakaiya
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Patent number: 10817441Abstract: The present disclosure is directed to systems and methods sharing memory circuitry between processor memory circuitry and accelerator memory circuitry in each of a plurality of peer-to-peer connected accelerator units. Each of the accelerator units includes virtual-to-physical address translation circuitry and migration circuitry. The virtual-to-physical address translation circuitry in each accelerator unit includes pages for each of at least some of the plurality of accelerator units. The migration circuitry causes the transfer of data between the processor memory circuitry and the accelerator memory circuitry in each of the plurality of accelerator circuits. The migration circuitry migrates and evicts data to/from accelerator memory circuitry based on statistical information associated with accesses to at least one of: processor memory circuitry or accelerator memory circuitry in one or more peer accelerator circuits.Type: GrantFiled: March 29, 2019Date of Patent: October 27, 2020Assignee: INTEL CORPORATIONInventors: Sanjay Kumar, David Koufaty, Philip Lantz, Pratik Marolia, Rajesh Sankaran, Koen Koning
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Publication number: 20200327256Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Applicant: INTEL CORPORATIONInventors: JOSHUA FENDER, UTKARSH Y. KAKAIYA, MOHAN NAIR, BRIAN MORRIS, PRATIK MAROLIA
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Publication number: 20200310993Abstract: The present disclosure is directed to systems and methods sharing memory circuitry between processor memory circuitry and accelerator memory circuitry in each of a plurality of peer-to-peer connected accelerator units. Each of the accelerator units includes physical-to-virtual address translation circuitry and migration circuitry. The physical-to-virtual address translation circuitry in each accelerator unit includes pages for each of at least some of the plurality of accelerator units. The migration circuitry causes the transfer of data between the processor memory circuitry and the accelerator memory circuitry in each of the plurality of accelerator circuits. The migration circuitry migrates and evicts data to/from accelerator memory circuitry based on statistical information associated with accesses to at least one of: processor memory circuitry or accelerator memory circuitry in one or more peer accelerator circuits.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Applicant: INTEL CORPORATIONInventors: Sanjay Kumar, David Koufaty, Philip Lantz, Pratik Marolia, Rajesh Sankaran, Koen Koning
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Patent number: 10762244Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.Type: GrantFiled: June 29, 2018Date of Patent: September 1, 2020Assignee: INTEL CORPORATIONInventors: Joshua Fender, Utkarsh Y. Kakaiya, Mohan Nair, Brian Morris, Pratik Marolia
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Publication number: 20200021540Abstract: In one embodiment, an input/output port includes a stateful transmit port having: a history storage to store a value corresponding to a transmit on change field of a prior data packet; a comparator to compare a transmit on change field of the data packet to the value stored in the history storage; and a selection circuit to output the data packet without the transmit on change field when the transmit on change field of the data packet matches the value. Other embodiments are described and claimed.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Inventors: Pratik Marolia, Rajesh Sankaran, Ishwar Agarwal, Nitish Paliwal
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Patent number: 10528768Abstract: Methods and apparatus to provide user-level access authorization for cloud-based filed-programmable gate arrays are disclosed. An example apparatus includes a field-programmable gate array (FPGA) including a first memory and a second memory different from the first memory. The first memory stores a bitstream. The second memory stores a first user tag associated with the bitstream. The example apparatus further includes a kernel having an FPGA driver operatively coupled to the FPGA. The FPGA driver is to receive a command associated with accessing the FPGA from a user-executed application. The FPGA driver is further to identify a second user tag associated with the command. The FPGA driver is further to determine whether the command is to be accepted based on the second user tag.Type: GrantFiled: September 15, 2017Date of Patent: January 7, 2020Assignee: INTEL CORPORATIONInventors: Suchit Subhaschandra, Srivatsan Krishnan, Brent Thomas, Pratik Marolia
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Publication number: 20190087606Abstract: Methods and apparatus to provide user-level access authorization for cloud-based filed-programmable gate arrays are disclosed. An example apparatus includes a field-programmable gate array (FPGA) including a first memory and a second memory different from the first memory. The first memory stores a bitstream. The second memory stores a first user tag associated with the bitstream. The example apparatus further includes a kernel having an FPGA driver operatively coupled to the FPGA. The FPGA driver is to receive a command associated with accessing the FPGA from a user-executed application. The FPGA driver is further to identify a second user tag associated with the command. The FPGA driver is further to determine whether the command is to be accepted based on the second user tag.Type: ApplicationFiled: September 15, 2017Publication date: March 21, 2019Inventors: Suchit Subhaschandra, Srivatsan Krishnan, Brent Thomas, Pratik Marolia
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Publication number: 20190042801Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.Type: ApplicationFiled: June 29, 2018Publication date: February 7, 2019Inventors: JOSHUA FENDER, UTKARSH Y. KAKAIYA, MOHAN NAIR, BRIAN MORRIS, PRATIK MAROLIA
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Publication number: 20190042329Abstract: A system is provided that includes a host processor coupled to a programmable acceleration coprocessor. The coprocessor may include logic for implementing a physical function and multiple associated virtual functions. The coprocessor may include a static programmable resource interface circuit (PIC) configured to perform management functions and one or more partial reconfiguration regions, each of which can be loaded with an accelerator function unit (AFU). An AFU may further be partitioned into AFU contexts (AFCs), each of which can be mapped to one of the virtual functions. The PIC enables hardware discovery/enumeration and loading of device drivers such that security isolation and interface performance are maintained.Type: ApplicationFiled: June 29, 2018Publication date: February 7, 2019Inventors: Utkarsh Y. Kakaiya, Pratik Marolia, Joshua David Fender, Sundar Nadathur, Nagabhushan Chitlur, Yuling Yang, David Alexander Munday