Abstract: Provided herein are techniques to facilitate automatic gain control for an optical receiver. In one example, a method may include for a first mode, first adjusting, for a received optical input signal, at least one of: a coarse gain of a programmable gain amplifier (PGA), a fine gain of the PGA, or an attenuation of a variable optical attenuator (VOA) until a voltage swing peak value of an output signal of the optical receiver satisfies a first voltage swing peak range. The method may further include, through a second mode, triggering second adjusting of at least one of the VOA attenuation or the PGA fine gain based on determining that the voltage swing peak value of the output signal does not satisfy a second voltage swing peak range or that another voltage swing peak value obtained from an external signal processing device does not satisfy another voltage swing peak range.

Abstract: Provided herein are techniques to facilitate automatic gain control for an optical receiver. In one example, a method may include for a first mode, first adjusting, for a received optical input signal, at least one of: a coarse gain of a programmable gain amplifier (PGA), a fine gain of the PGA, or an attenuation of a variable optical attenuator (VOA) until a voltage swing peak value of an output signal of the optical receiver satisfies a first voltage swing peak range. The method may further include, through a second mode, triggering second adjusting of at least one of the VOA attenuation or the PGA fine gain based on determining that the voltage swing peak value of the output signal does not satisfy a second voltage swing peak range or that another voltage swing peak value obtained from an external signal processing device does not satisfy another voltage swing peak range.

Abstract: A circuit generates a system clock signal. On a first input of the circuit a first oscillating signal is placed. On a second input, a second oscillating signal may be placed. Clock sense logic is connected to the second input. The clock sense logic detects whether the second oscillation signal is present on the second input. When the second oscillating signal is not present on the second input, the first oscillating signal is selected to be used to generate the system clock. When the second oscillating signal is present on the second input, the second oscillating signal is selected to be used to generate the system clock. The selected oscillating signal is divided to produce the system clock signal. A first frequency divider divides the selected oscillating signal by a first amount. In parallel, a second frequency divider divides the selected oscillating signal by a second amount.