Patents by Inventor Pratyush Aditya Kothamasu

Pratyush Aditya Kothamasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power and scan resource reduction in integrated circuit designs having shift registers
    Patent number: 10417363
    Abstract: Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: September 17, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Jagjot Kaur, Priyanka Dasgupta, Pratyush Aditya Kothamasu, Vivek Chickermane