Patents by Inventor Pravas Pradhan
Pravas Pradhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9984654Abstract: A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.Type: GrantFiled: May 15, 2017Date of Patent: May 29, 2018Assignee: INTEL CORPORATIONInventors: Aruna Kumar, Prakash K. Radhakrishnan, Pravas Pradhan, Sunil Kumar C R, Vikas J
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Publication number: 20170249922Abstract: A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Inventors: ARUNA KUMAR, PRAKASH K. RADHAKRISHNAN, PRAVAS PRADHAN, SUNIL KUMAR C. R., VIKAS J.
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Patent number: 9653040Abstract: A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.Type: GrantFiled: November 22, 2016Date of Patent: May 16, 2017Assignee: Intel CorporationInventors: Aruna Kumar, Prakash K. Radhakrishnan, Pravas Pradhan, Sunil Kumar C R, Vikas J
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Patent number: 9612647Abstract: By partitioning the source PHY of a physical layer interface, such as a DisplayPort interface, between multiple power domains, dynamic switching between various power modes with faster entry and exit latency can be achieved in some embodiments. In some embodiments, the scheme may be hardware initiated and autonomous in nature. A controller can switch the PHY in and out of the various power consumption modes, dependent on usage scenarios.Type: GrantFiled: November 8, 2013Date of Patent: April 4, 2017Assignee: Intel CorporationInventors: Sathyanarayanan Gopal, Sanjib Basu, Pravas Pradhan, Prakash K. Radhakrishnan
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Publication number: 20170076689Abstract: A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.Type: ApplicationFiled: November 22, 2016Publication date: March 16, 2017Inventors: ARUNA KUMAR, PRAKASH K. RADHAKRISHNAN, PRAVAS PRADHAN, SUNIL KUMAR C R, VIKAS J
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Patent number: 9503288Abstract: A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.Type: GrantFiled: December 27, 2013Date of Patent: November 22, 2016Assignee: Intel CorporationInventors: Aruna Arun Kumar, Prakash K. Radhakrishnan, Pravas Pradhan, Sunil Kumar C R, Vikas J.
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Publication number: 20150186091Abstract: A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Inventors: Aruna Arun Kumar, Prakash K. Radhakrishnan, Pravas Pradhan, Sunil Kumar C R, Vikas J.
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Publication number: 20150134985Abstract: By partitioning the source PHY of a physical layer interface, such as a DisplayPort interface, between multiple power domains, dynamic switching between various power modes with faster entry and exit latency can be achieved in some embodiments. In some embodiments, the scheme may be hardware initiated and autonomous in nature. A controller can switch the PHY in and out of the various power consumption modes, dependent on usage scenarios.Type: ApplicationFiled: November 8, 2013Publication date: May 14, 2015Inventors: Sathyanarayanan Gopal, Sanjib Basu, Pravas Pradhan, Prakash K. Radhakrishnan
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Publication number: 20150092065Abstract: A method for training the lanes of a main data link includes setting an initial lane voltage swing and conducting link at the initial value, and determining if link training was successful. If link training at the initial value of lane voltage swing was not successful, the value of lane voltage swing is incremented to a predetermined value. A determination is made as to whether the predetermined value of lane voltage swing exceeds a threshold value, and link training is ended if the predetermined value of lane voltage exceeds the threshold value. If the predetermined value of lane voltage swing does not exceed the threshold value, link training is conducted at the predetermined value of lane voltage swing until link training is successful or until a predetermined number of attempts at the predetermined value of lane voltage swing fail to successfully train the link.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Inventors: Prakash Radhakrishnan, Sathyanarayanan Gopal, Pravas Pradhan, Aruna Kumar
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Publication number: 20150085187Abstract: An electronic device, method, and at least one machine readable medium for burst mode processing of video data with inband link power management are provided herein. The method includes receiving a pixel stream, transferring the received stream as currently-available frame-formatted video data to a sink in burst at high data rate, and entering a reduced-power operating state until transfer of additional currently-available video data is enabled. The method may include issuing inband command signals to cause the link to enter into and exit from the reduced-power link operating states.Type: ApplicationFiled: September 20, 2013Publication date: March 26, 2015Inventors: Huimin Chen, George R. Hayek, Robert Jamie Johnston, Pravas Pradhan, Satyanarayana Avadhanam, Seh W. Kwa
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Patent number: 8912823Abstract: Described herein is a voltage compensated level-shifter with nearly constant duty cycle and matching rise and fall slopes of the output of the level-shifter, no meta-stability, and nearly constant propagation delay across power supply levels. The voltage compensated level-shifter comprises a first inverter to receive an input signal for level shifting from a first power supply level to a second power supply level, and to generate a first inverted signal, the first inverter operating on the first power supply level; a second inverter to receive the input signal and to generate a second inverted signal, the second inverter operating on the second power supply level; and a NOR logical gate to receive the first and second inverted signals and to generate an output signal, the NOR logical gate operating on the second power supply level, wherein the output signal is level shifted to the second power supply level.Type: GrantFiled: December 8, 2011Date of Patent: December 16, 2014Assignee: Intel CorporationInventors: Venkatesh Rao, Alok Shah, Pravas Pradhan
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Publication number: 20130321026Abstract: Described herein is a voltage compensated level-shifter with nearly constant duty cycle and matching rise and fall slopes of the output of the level-shifter, no meta-stability, and nearly constant propagation delay across power supply levels. The voltage compensated level-shifter comprises a first inverter to receive an input signal for level shifting from a first power supply level to a second power supply level, and to generate a first inverted signal, the first inverter operating on the first power supply level; a second inverter to receive the input signal and to generate a second inverted signal, the second inverter operating on the second power supply level; and a NOR logical gate to receive the first and second inverted signals and to generate an output signal, the NOR logical gate operating on the second power supply level, wherein the output signal is level shifted to the second power supply level.Type: ApplicationFiled: December 8, 2011Publication date: December 5, 2013Inventors: Venkatesh Rao, Alok Shah, Pravas Pradhan
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Patent number: 8595274Abstract: Generally, this disclosure describes a system and method for generating random numbers. In at least one embodiment described herein, the method may include generating random bits in accordance with at least one security application via an integrated circuit, said integrated circuit including a true random number generator having an analog core. The method may further include providing, via an internally generated power supply, power to said analog core via a voltage regulator associated with said true random number generator. Of course, additional operations are also within the scope of the present disclosure.Type: GrantFiled: December 31, 2007Date of Patent: November 26, 2013Assignee: Intel CorporationInventors: Pravas Pradhan, Andrew M. Volk, Praveen Dani
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Publication number: 20090172056Abstract: Generally, this disclosure describes a system and method for generating random numbers. In at least one embodiment described herein, the method may include generating random bits in accordance with at least one security application via an integrated circuit, said integrated circuit including a true random number generator having an analog core. The method may further include providing, via an internally generated power supply, power to said analog core via a voltage regulator associated with said true random number generator. Of course, additional operations are also within the scope of the present disclosure.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Applicant: INTEL CORPORATIONInventors: Pravas Pradhan, Andrew M. Volk, Praveen Dani
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Patent number: 7154307Abstract: A current mode transfer logic system suitable for driving transmission lines is disclosed. In one embodiment a twisted pair transmission line is terminated in its characteristic line impedance. A signal is formed of two unequal currents, preferably of different polarities as well as magnitudes, that are driven down the two lines. The unequal currents are selectively switched between the two lines creating a logic signal of a differential current drive of unequal current magnitudes. The unequal currents are received and shunted from the distal end of each line via diode connected MOS transistors. The MOS transistors are biased to present a low impedance, but an impedance higher than the terminating resistor. The currents are amplified and converted to useable CMOS voltage levels. In another embodiment the twisted pair is replaced by two parallel transmission lines which are terminated in one resistor, equal to the sum of the characteristic impedances of each line.Type: GrantFiled: November 24, 2003Date of Patent: December 26, 2006Assignee: Fairchild Semiconductor CorporationInventors: Pravas Pradhan, Jianhong Ju
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Patent number: 6970043Abstract: A folded common cascode circuit with symmetric parallel signal paths from the differential inputs to a single ended output provides a low skew, low jitter, low power, high speed differential amplifier. The signal paths on either side of the differential amplifier are made equal with equal loads along each path. Pairs of complementary NMOS and PMOS transistor pairs with parallel complementary biasing current mirroring stacks on the cascode circuitry have all their gates connected together. The layout maintains symmetrical parallel signal paths and symmetrical amplification and impedance loading from differential input to output. Output inverters provide a higher drive capability.Type: GrantFiled: August 21, 2003Date of Patent: November 29, 2005Assignee: Fairchild Semiconductor CorporationInventors: Pravas Pradhan, Shailesh Chitnis
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Patent number: 6927599Abstract: A system and method are described for receiving differential currents in a current mode circuit. When conditions occur where the receiver inputs are floating, undriven, shorted together, or one or both shorted to ground, the output of the system remains stable. Diode connected MOS transistors receive the unequal currents, and current mirrors amplify the received currents. Those amplified mirrored currents are differentially amplified and converted into voltage signals suitable of typical computer and logic systems. The current mode differential nature of the invention provides high common mode current and voltage noise immunity. A threshold for the unequal currents helps provide high differential current and voltage noise immunity.Type: GrantFiled: November 24, 2003Date of Patent: August 9, 2005Assignee: Fairchild Semiconductor CorporationInventors: Jianhong Ju, Pravas Pradhan
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Publication number: 20050110529Abstract: A current mode transfer logic system suitable for driving transmission lines is disclosed. In one embodiment a twisted pair transmission line is terminated in its characteristic line impedance. A signal is formed of two unequal currents, preferably of different polarities as well as magnitudes, that are driven down the two lines. The unequal currents are selectively switched between the two lines creating a logic signal of a differential current drive of unequal current magnitudes. The unequal currents are received and shunted from the distal end of each line via diode connected MOS transistors. The MOS transistors are biased to present a low impedance, but an impedance higher than the terminating resistor. The currents are amplified and converted to useable CMOS voltage levels. In another embodiment the twisted pair is replaced by two parallel transmission lines which are terminated in one resistor, equal to the sum of the characteristic impedances of each line.Type: ApplicationFiled: November 24, 2003Publication date: May 26, 2005Inventors: Pravas Pradhan, Jianhong Ju
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Publication number: 20050110515Abstract: A system and method are described for receiving differential currents in a current mode circuit. When condition occur where the receiver inputs are floating, undriven, shorted together, or one or both shorted to ground, the output of the system remains stable. Diode connected MOS transistors receive the unequal currents, and current mirrors amplify the received currents. Those amplified mirrored currents are differentially amplified and converted into voltage signals suitable of typical computer and logic systems. The current mode differential nature of the invention provides high common mode current and voltage noise immunity. A threshold for the unequal currents helps provide high differential current and voltage noise immunity.Type: ApplicationFiled: November 24, 2003Publication date: May 26, 2005Inventors: Jianhong Ju, Pravas Pradhan
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Patent number: 6870424Abstract: A folded common cascode circuit with symmetric parallel signal paths from the differential inputs to a single ended output provides a low skew, low jitter, low power, high speed differential in/out amplifier. There is a differential input stage followed by a load or current summation stage with all gates tied together, and then a second differential stage. The dynamic voltage range of the second stage allows for lower Vcc operation while providing improved jitter operation. The signal paths on either side of the differential amplifier are made equal with equal loads along each path. Pairs of complementary NMOS and PMOS transistor pairs with parallel complementary biasing current mirroring stacks on the cascode circuitry have all their gates connected together. The layout maintains symmetrical parallel signal paths and symmetrical amplification and impedance loading from differential input to the differential output. Output inverters provide a higher drive capability.Type: GrantFiled: August 21, 2003Date of Patent: March 22, 2005Assignee: Fairchild Semiconductor CorporationInventors: Pravas Pradhan, Shailesh Chitnis