Abstract: The invention relates to a method (100) for an automated generation of synthetic scenes (175), comprising the following steps: providing (101) scene data (110) representing a plurality of template scenes (120), providing (102) object data (115) specifying various objects (125) for insertion into the synthetic scene (175), providing (103) at least one scene parameter (130) for the template scenes (120), which describes at least one characteristic of the template scenes (120), generating (106) intermediate representations (140) for the synthetic scenes (175), wherein, regarding the intermediate representations (140), at least one selected object (125) is in each case inserted into a selected template scene (120), wherein the insertion of the at least one selected object (125) is parametrized based on the provided scene parameter (130) in order to account for physical plausibility in the respective intermediate representation (140), determining (107) conditioning data (150) from the generated intermediate rep

Abstract: A scatter gather cache system and method are provided, which increase performance of scatter-gather DMA operations by reducing the time taken by the DMA engine to perform a logical to physical address translation. This is done primarily by two-dimensional caching of scatter-gather elements of selected scatter-gather lists using a novel indexing, line swapping and replacement methodology. The cache can also include a context victim table (CVT) for storing scatter-gather list contexts from evicted cache entries and also allows for pre-fetching of SGL elements from Scatter-Gather Lists (SGL). It also provides coherency support when there are multiple instances of the cache accessing the same memory space.

Abstract: A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.

Abstract: A scatter gather element based caching system is provided along with a modified scatter gather element, that supports efficient logical to physical address translation for arbitrarily aligned and arbitrarily sized fragment (segment) based memory management schemes. This is different from modern CPU implementations with MMUs that support page-based implementations. A primary application of embodiments of the present invention is in DMA applications. The system enables frequent switching of contexts between I/Os using a novel caching technique. An embodiment of the present invention also includes the modification of the conventional scatter-gather element used in DMA for supporting multiple memory spaces, backward list traversals, better error recovery and debugging.

Abstract: A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.