Patents by Inventor Praveen Alexander

Praveen Alexander has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8495301
    Abstract: A scatter gather cache system and method are provided, which increase performance of scatter-gather DMA operations by reducing the time taken by the DMA engine to perform a logical to physical address translation. This is done primarily by two-dimensional caching of scatter-gather elements of selected scatter-gather lists using a novel indexing, line swapping and replacement methodology. The cache can also include a context victim table (CVT) for storing scatter-gather list contexts from evicted cache entries and also allows for pre-fetching of SGL elements from Scatter-Gather Lists (SGL). It also provides coherency support when there are multiple instances of the cache accessing the same memory space.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: July 23, 2013
    Assignee: PMC-Sierra US, Inc.
    Inventors: Praveen Alexander, Cheng Yi, Tao Zhong, David J. Clinton, Gary Nichols
  • Patent number: 8271700
    Abstract: A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: September 18, 2012
    Assignee: PMC-Sierra US, Inc.
    Inventors: Babysaroja Annem, David J. Clinton, Praveen Alexander
  • Patent number: 8176252
    Abstract: A scatter gather element based caching system is provided along with a modified scatter gather element, that supports efficient logical to physical address translation for arbitrarily aligned and arbitrarily sized fragment (segment) based memory management schemes. This is different from modern CPU implementations with MMUs that support page-based implementations. A primary application of embodiments of the present invention is in DMA applications. The system enables frequent switching of contexts between I/Os using a novel caching technique. An embodiment of the present invention also includes the modification of the conventional scatter-gather element used in DMA for supporting multiple memory spaces, backward list traversals, better error recovery and debugging.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: May 8, 2012
    Assignee: PMC-Sierra US, Inc.
    Inventors: Praveen Alexander, Heng Liao
  • Patent number: 7877524
    Abstract: A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: January 25, 2011
    Assignee: PMC-Sierra US, Inc.
    Inventors: Babysaroja Annem, Heng Liao, Zhongzhi Liu, Praveen Alexander