Patents by Inventor Praveen Jain

Praveen Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070096703
    Abstract: The invention relates to a dynamic conversion circuit for improving the transient response of a switching DC-DC converter, such as in a voltage regulator module (VRM). The dynamic conversion circuit may be applied to a single phase or multiphase interleaved VRM of either isolated or non-isolated design configurations, and enhances power transfer from the input to the output of the DC-DC converter and tightly regulates the output voltage during harsh load current transients.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 3, 2007
    Inventor: Praveen Jain
  • Publication number: 20070096704
    Abstract: A digital controller for a voltage regulator module (VRM) having single phase or multiphase power converters, and an optional dynamic conversion circuit, is disclosed. The digital controller improves the transient response of the VRM during harsh load current transients, and permits a substantial reduction in output capacitance of the VRM. When used with multiphase interleaved power converters, for a given load current requirement, the digital converter permits the number of interleaved phases of the VRM to be minimized. A VRM with the digital controller demonstrates low cost, high power density, high efficiency, and fast transient response.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 3, 2007
    Inventors: Praveen Jain, Wennan Guo
  • Publication number: 20060092932
    Abstract: N_Ports and F_Ports are provided with logic allowing designation of multiple virtual interfaces on a single host bus adaptor or other Fibre Channel interface, one virtual interface for each VSAN operating on the node interface. Node ports with this additional functionality are referred to as trunking N_Ports or TN_Ports. These ports have a functional design allowing creation of the multiple virtual interfaces as appropriate for the application at hand. This port design also includes logic for communicating with a peer fabric port to initialize and modify the configuration of the virtual interfaces on the TN_Port. A corresponding functional design and communication logic is provided for fabric ports, referred to herein as trunking F_Ports or TF_Ports.
    Type: Application
    Filed: November 1, 2004
    Publication date: May 4, 2006
    Inventors: Kalyan Ghosh, Praveen Jain, Shashank Gupta, Tushar Desai
  • Publication number: 20060087963
    Abstract: A port shutdown protocol coordinates among various components involved in the process of administratively bringing down a link at both ends of a link connecting two switches. Execution of the protocol avoids or reduces frame drops and/or reordering. In this protocol, peer switches perform various actions when bringing down an ISL in a synchronized manner. In one implementation, this protocol uses the Exchange Peer Protocol (EPP) as the underlying transport to carry the port shutdown protocol frames.
    Type: Application
    Filed: October 25, 2004
    Publication date: April 27, 2006
    Inventors: Praveen Jain, Ranganathan Rajagopalan, Ramsundar Janakiraman, Shashank Gupta, Sachin Jain
  • Publication number: 20060039366
    Abstract: According to the present invention, methods and apparatus are provided to allow efficient and effective aggregation of ports into port channels in a fibre channel network. A local fibre channel switch can automatically identify compatible ports and initiate exchange sequences with a remote fibre channel switch to aggregate ports into port channels. Ports can be aggregated synchronously to allow consistent generation of port channel map tables.
    Type: Application
    Filed: August 20, 2004
    Publication date: February 23, 2006
    Applicant: Cisco Technology, Inc.
    Inventors: Kalyan Ghosh, Praveen Jain, Shankar Subramaniam, Rajesh Bhandari, Prabesh Nanjundaiah
  • Publication number: 20040100910
    Abstract: Methods and devices are provided for detecting whether peer ports interconnecting two network devices can perform a novel protocol called Exchange Peer Parameters (“EPP”). If the peer ports are so configured to perform EPP, EPP services are exchanged between the peer ports. In a first phase, information is exchanged about peer port configurations of interest. In a second phase, the results of the exchange of information are applied to hardware and/or software of the respective ports, as needed.
    Type: Application
    Filed: May 5, 2003
    Publication date: May 27, 2004
    Applicant: Andiamo Systems, Inc.
    Inventors: Tushar Desai, Shashank Gupta, Praveen Jain, Kalyan K. Ghosh
  • Patent number: 6628624
    Abstract: A method and apparatus facilitates and enhances the operation of the spanning tree protocol in bridged computer networks. An intermediate network device in accordance with the present invention includes an enhanced spanning tree engine that is configured to perform certain novel functions. First, the enhanced spanning tree engine is configured to identify and block ports at which messages are looped-back to the transmitting port, thereby avoiding the creation of network loops. In second aspect, the enhanced spanning tree engine rapidly transitions certain ports to a forwarding state to prevent associated applications from timing out and shutting down. Rather than moving the ports through blocking, listening and learning states before reaching the forwarding state, selected ports may be transitioned directly to the forwarding state.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: September 30, 2003
    Assignee: Cisco Technology, Inc.
    Inventors: Umesh Mahajan, Ramana Mellacheruvu, Praveen Jain
  • Patent number: 6407985
    Abstract: In order to load share non-configuration message traffic on more than one port of a non-root spanning tree protocol compliant switching node, upon receiving a spanning tree algorithm port-blocking message, the switching node assigns a port filter to each of its non-designated ports. The switching node then directs a spanning tree non-configuration message through a port that has a port filter which corresponds to the non-configuration message. The switching node may be implemented using any learning switch, or equivalent device, which complies with a spanning tree algorithm, has sufficient memory to store the port filters used, a means for applying the port filters to its non-designated ports, and a means for directing at least one spanning tree non-configuration message to a port having a port filter that corresponds to the non-configuration message. The switching node may be implemented on any spanning tree compliant network, such as a IEEE 802.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: June 18, 2002
    Assignee: Cisco Technology, Inc.
    Inventor: Praveen Jain
  • Patent number: 6304575
    Abstract: An improved spanning tree protocol for use by token ring intermediate devices having one or more Concentrator Relay Function (CRF) entities and associated Bridge Relay Function (BRF) entities. Each CRF and BRF entity preferably includes a spanning tree engine and corresponding database for individually executing an instance of the spanning tree algorithm and is configured to select a different Bridge Protocol Data Unit (BPDU) message type for use in executing its respective spanning tree algorithm. The selection of BPDU message type by the CRF and BRF spanning tree engines preferably depends on the routing configuration of the associated CRF. The selection of BPDU message type by the CRF entities assures that they are dropped by legacy intermediate devices and only acted upon by the originating CRF or another CRF coupled thereto.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: October 16, 2001
    Assignee: Cisco Technology, Inc.
    Inventors: David A. Carroll, Kara J. Adams, Kenneth H. Potter, Jr., Praveen Jain
  • Patent number: 6097614
    Abstract: An asymmetrical pulse width modulated resonant DC--DC converter exhibiting improved zero voltage switching characteristics is disclosed. The converter includes a chopper circuit to convert the DC input voltage to a high frequency AC voltage which, in turn, is fed to a high frequency transformer whose secondary AC is rectified and filtered to produce a stable DC output. A compensation network is placed between the input and the chopper circuit which provides zero voltage switching of the converter over a wide input voltage range.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: August 1, 2000
    Assignee: Astec International Limited
    Inventors: Praveen Jain, Yan-Fei Liu, Simmi Mangat
  • Patent number: 5665296
    Abstract: A method for assembling a plastic integrated circuit package. The method includes placing an integrated circuit die and lead frame into a mold. The mold has a first gate that is in fluid communication with a first side of the lead frame and a second opposite gate which is in fluid communication with a second side of the lead frame. The lead frame also has a mold flow hole adjacent to the gates. A plastic encapsulant is injected into both gates and flows across each side of the lead frame. The mold flow opening allows encapsulant to flow between each side of the lead frame.
    Type: Grant
    Filed: December 12, 1995
    Date of Patent: September 9, 1997
    Assignee: Intel Corporation
    Inventors: Praveen Jain, Rudra Kar
  • Patent number: 5475569
    Abstract: An electronic package that is tested before the leads of the package are cut and bent into a final shape. The electronic package has a plurality of leads that extend from an outer housing of the package. The package is typically rectangular in shape and has a group of leads extending from each side of the housing. Extending along each group of leads is a strip of dielectric material that is spaced an offset distance from the side of the housing. The package is tested by placing a plurality of corresponding test pins into contact with the leads over their final cut and formed length in an area between the housing and the dielectric strip. The area of contact corresponds to the ends of the final assembled leads, so that the actual impedance of the leads over their final cut and formed length are tested. The dielectric strip provides structural support for the leads during the handling and testing of the package.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: December 12, 1995
    Assignee: Intel Corporation
    Inventors: Praveen Jain, Steve Prough
  • Patent number: 5444602
    Abstract: An electronic package which has a heat sink that is attached to the lead frame of the package with a material that is both electrically and thermally conductive. The lead frame is also coupled to a first surface of an integrated circuit die with tape automated bonded (TAB) leads. The low thermal resistance of the heat sink increases the thermal performance of the package. The heat sink may also be mounted directly to the die with a conductive material so that the die is electrically grounded to the heat sink. The heat sink is then bonded to the leads of the lead frame that are dedicated to ground. In this embodiment, the heat sink provides the dual functions of a ground plate and a heat spreader.
    Type: Grant
    Filed: February 25, 1994
    Date of Patent: August 22, 1995
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Siva Natarajan, Debendra Mallik, Praveen Jain