Patents by Inventor Praveen JOGINIPALLY

Praveen JOGINIPALLY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11893423
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 6, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Sonata Gale Wen, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Publication number: 20230289212
    Abstract: Processing hardware of a processor is virtualized to provide a façade between a consistent programming interface and specific hardware instances. Hardware processor components can be permanently or temporarily disabled when not needed to support the consistent programming interface and/or to balance hardware processing across a hardware arrangement such as an integrated circuit. Executing software can be migrated from one hardware arrangement to another without need to reset the hardware.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Inventors: Jerome F. DULUK, JR., Gentaro HIROTA, Ronny KRASHINSKY, Greg PALMER, Jeff TUCKEY, Kaushik NADADHUR, Philip Browning JOHNSON, Praveen JOGINIPALLY
  • Publication number: 20230288471
    Abstract: Processing hardware of a processor is virtualized to provide a façade between a consistent programming interface and specific hardware instances. Hardware processor components can be permanently or temporarily disabled when not needed to support the consistent programming interface and/or to balance hardware processing across a hardware arrangement such as an integrated circuit. Executing software can be migrated from one hardware arrangement to another without need to reset the hardware.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Inventors: Jerome F. DULUK, Gentaro HIROTA, Ronny KRASHINSKY, Greg PALMER, Jeff TUCKEY, Kaushik NADADHUR, Philip Browning JOHNSON, Praveen JOGINIPALLY
  • Patent number: 11720440
    Abstract: Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: August 8, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Naveen Cherukuri, Saurabh Hukerikar, Paul Racunas, Nirmal Raj Saxena, David Charles Patrick, Yiyang Feng, Abhijeet Ghadge, Steven James Heinrich, Adam Hendrickson, Gentaro Hirota, Praveen Joginipally, Vaishali Kulkarni, Peter C. Mills, Sandeep Navada, Manan Patel, Liang Yin
  • Patent number: 11663036
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: May 30, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Eric Rock, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Patent number: 11635986
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 25, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Eric Rock, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Patent number: 11579925
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 14, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Eric Rock, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Publication number: 20230011863
    Abstract: Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.
    Type: Application
    Filed: July 12, 2021
    Publication date: January 12, 2023
    Inventors: NAVEEN CHERUKURI, SAURABH HUKERIKAR, PAUL RACUNAS, NIRMAL RAJ SAXENA, DAVID CHARLES PATRICK, YIYANG FENG, ABHIJEET GHADGE, STEVEN JAMES HEINRICH, ADAM HENDRICKSON, GENTARO HIROTA, PRAVEEN JOGINIPALLY, VAISHALI KULKARNI, PETER C. MILLS, SANDEEP NAVADA, MANAN PATEL, LIANG YIN
  • Patent number: 11249905
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 15, 2022
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Eric Rock, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Publication number: 20210157651
    Abstract: A parallel processing unit (PPU), operating in a traditional processing environment or in a virtualized processing environment, can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Application
    Filed: February 1, 2021
    Publication date: May 27, 2021
    Inventors: Jerome F. DULUK, Jr., Gregory Scott PALMER, Jonathon Stuart Ramsay EVANS, Shailendra SINGH, Samuel H. DUNCAN, Wishwesh Anil GANDHI, Lacky V. SHAH, Eric ROCK, Feiqi SU, James Leroy DEMING, Alan MENEZES, Pranav VAIDYA, Praveen JOGINIPALLY, Timothy John PURCELL, Manas MANDAL
  • Publication number: 20210073025
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Jerome F. DULUK, JR., Gregory Scott PALMER, Jonathon Stuart Ramsey EVANS, Shailendra SINGH, Samuel H. DUNCAN, Wishwesh Anil GANDHI, Lacky V. SHAH, Eric ROCK, Feiqi SU, James Leroy DEMING, Alan MENEZES, Pranav VAIDYA, Praveen JOGINIPALLY, Timothy John PURCELL, Manas MANDAL
  • Publication number: 20210073125
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Jerome F. DULUK, JR., Gregory Scott PALMER, Jonathon Stuart Ramsey EVANS, Shailendra SINGH, Samuel H. DUNCAN, Wishwesh Anil GANDHI, Lacky V. SHAH, Eric ROCK, Feiqi SU, James Leroy DEMING, Alan MENEZES, Pranav VAIDYA, Praveen JOGINIPALLY, Timothy John PURCELL, Manas MANDAL
  • Publication number: 20210073035
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Jerome F. DULUK, Jr., Gregory Scott PALMER, Jonathon Stuart Ramsey EVANS, Shailendra SINGH, Samuel H. DUNCAN, Wishwesh Anil GANDHI, Lacky V. SHAH, Eric ROCK, Feiqi SU, James Leroy DEMING, Alan MENEZES, Pranav VAIDYA, Praveen JOGINIPALLY, Timothy John PURCELL, Manas MANDAL
  • Publication number: 20210073042
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Jerome F. DULUK, Jr., Gregory Scott PALMER, Jonathon Stuart Ramsey EVANS, Shailendra SINGH, Samuel H. DUNCAN, Wishwesh Anil GANDHI, Lacky V. SHAH, Eric ROCK, Feiqi SU, James Leroy DEMING, Alan MENEZES, Pranav VAIDYA, Praveen JOGINIPALLY, Timothy John PURCELL, Manas MANDAL