Abstract: A system and method for efficiently performing a data encryption operation in an electronic system preferably includes a processor that may initially create an encryption structure in a memory device. The encryption structure may preferably include one or more command structures for performing data encryption or decryption operations. The processor may subsequently program local control registers of a DMA engine with selected encryption information in response to a data encryption or decryption requirement. The processor may then instruct the DMA engine to perform the required data encryption or decryption operation. Next, the DMA engine may responsively copy one or more of the command structures from the memory device into local command registers that are coupled to the DMA engine. The DMA engine may then reference the foregoing control registers and command registers to thereby efficiently perform one or more data encryption or decryption operations.

Abstract: An apparatus and method for efficiently performing data transfer operations in an electronic system preferably includes a plurality of buffers that may store data and commands during execution of data transfer operations. Initially, at least a portion of a plurality of commands defining data transfer operations between a memory and peripheral devices may be temporarily stored in a command buffer associated with a processor interface. The processor interface may then issue commands directly to a memory interface, peripheral devices, and peripheral interfaces within the electronic system. Commands received by the memory interface may be temporarily stored in a command buffer associated with the memory interface. When a memory associated with the memory interface is ready, the memory interface may access the memory, and transfer data to or from one or more buffers associated with a peripheral device.

Abstract: A system and method for efficiently performing a command swapping procedure may preferably include a processor configured to generate commands corresponding to various peripheral devices in an electronic system. A command queue may receive the foregoing commands from the processor, and may responsively store the commands into a FIFO memory device that may be configured to temporarily store the commands in a series of sequential memory locations. The peripheral devices may then repeatedly access the commands from a first location of the FIFO memory device when the corresponding peripheral devices are ready to execute the commands. Swap logic from the command queue may advantageously exchange a delayed command corresponding to a busy peripheral device, and substitute a non-delayed command for a non-busy peripheral device into the first location of the FIFO memory device to thereby permit the non-delayed command to be executed in a more expeditious and efficient manner.

Abstract: An apparatus and method for efficiently performing data transfer operations in an electronic system preferably includes a plurality of buffers that may store data and commands during execution of data transfer operations. Initially, at least a portion of a plurality of commands defining data transfer operations between a memory and peripheral devices may be temporarily stored in a command buffer associated with a processor interface. The processor interface may then issue commands directly to a memory interface, peripheral devices, and peripheral interfaces within the electronic system. Commands received by the memory interface may be temporarily stored in a command buffer associated with the memory interface. When a memory associated with the memory interface is ready, the memory interface may access the memory, and transfer data to or from one or more buffers associated with a peripheral device.

Abstract: A system and method for efficiently performing a data transfer operation in an electronic system preferably includes a processor that may initially create a DMA structure in a block transfer memory device. The DMA structure may preferably include one or more command structures for performing DMA data transfer operations. The processor may subsequently program local control registers of a DMA engine with selected DMA transfer information in response to a DMA data transfer requirement. The processor may then instruct the DMA engine to perform the required DMA data transfer operation. Next, the DMA engine may responsively copy one or more of the command structures from the block transfer memory device into local command registers that are coupled to the DMA engine. The DMA engine may then reference the foregoing control registers and command registers to thereby efficiently perform one or more DMA data transfer operations.

Abstract: A system and method for efficiently performing a data encryption operation in an electronic system preferably includes a processor that may initially create an encryption structure in a memory device. The encryption structure may preferably include one or more command structures for performing data encryption or decryption operations. The processor may subsequently program local control registers of a DMA engine with selected encryption information in response to a data encryption or decryption requirement. The processor may then instruct the DMA engine to perform the required data encryption or decryption operation. Next, the DMA engine may responsively copy one or more of the command structures from the memory device into local command registers that are coupled to the DMA engine. The DMA engine may then reference the foregoing control registers and command registers to thereby efficiently perform one or more data encryption or decryption operations.