Patents by Inventor Praveen K. Parvathala

Praveen K. Parvathala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Enabling at speed application of test patterns associated with a wide tester interface on a low pin count tester
    Patent number: 6990621
    Abstract: According to some embodiments, at speed application of test patterns associated with a wide tester interface are enabled on a low pin count tester. For example, an integrated circuit might include a processor core to exchange information via input and output paths (e.g., the paths might be associated with a bus external to the integrated circuit). The integrated circuit might also include a cache structure to store test information and a sequencer to transfer the test information from the cache structure. According to some embodiments, a multiplexer receives sets of signals from (i) at least a portion of the bus and (ii) the sequencer. Moreover, the multiplexer might provide one of the received sets of signals to the processor core via the input paths.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: January 24, 2006
    Assignee: Intel Corporation
    Inventors: Kailasnath S. Maneparambil, Praveen K. Parvathala
  • Functional random instruction testing (FRIT) method for complex devices such as microprocessors
    Patent number: 6948096
    Abstract: A functional random instruction testing (FRIT) method is provided for testing complex devices.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: September 20, 2005
    Assignee: Intel Corporation
    Inventors: Praveen K. Parvathala, Kailasnath Maneparambil, William C. Lindsay
  • Tool for generating a re-generative functional test
    Patent number: 6928638
    Abstract: A host system for generating a software built-in self-test engine (SBE) is provided for enabling on-chip generation and application of a re-generative functional test on a complex device such as a microprocessor under test. The host system comprises user directives provided to indicate user desired actions; instruction information provided to define a suite of instructions; and a SBE generation tool arranged to generate a software built-in self-test engine (SBE) based on the user directives, the instruction information and device constraints, for subsequent storage on-board of a complex device such as a microprocessor under test and activation of a re-generative functional test on the complex device under test (DUT).
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: August 9, 2005
    Assignee: Intel Corporation
    Inventors: Praveen K. Parvathala, Kailasnath Maneparambil, William C. Lindsay, Kamalnayan Jayaraman, Geliang Zhou
  • Enabling at speed application of test patterns associated with a wide tester interface on a low pin count tester
    Publication number: 20040153799
    Abstract: According to some embodiments, at speed application of test patterns associated with a wide tester interface are enabled on a low pin count tester.
    Type: Application
    Filed: December 20, 2002
    Publication date: August 5, 2004
    Inventors: Kailasnath S. Maneparambil, Praveen K. Parvathala
  • Functional random instruction testing (FRIT) method for complex devices such as microprocessors
    Publication number: 20030066003
    Abstract: A functional random instruction testing (FRIT) method is provided for testing complex devices.
    Type: Application
    Filed: July 31, 2001
    Publication date: April 3, 2003
    Inventors: Praveen K. Parvathala, Kailasnath Maneparambil, William C. Lindsay
  • Tool for generating a re-generative functional test
    Publication number: 20030033558
    Abstract: A host system for generating a software built-in self-test engine (SBE) is provided for enabling on-chip generation and application of a re-generative functional test on a complex device such as a microprocessor under test. The host system comprises user directives provided to indicate user desired actions; instruction information provided to define a suite of instructions; and a SBE generation tool arranged to generate a software built-in self-test engine (SBE) based on the user directives, the instruction information and device constraints, for subsequent storage on-board of a complex device such as a microprocessor under test and activation of a re-generative functional test on the complex device under test (DUT).
    Type: Application
    Filed: August 7, 2001
    Publication date: February 13, 2003
    Inventors: Praveen K. Parvathala, Kailasnath Maneparambil, William C. Lindsay, Kamalnayan Jayaraman, Geliang Zhou