Patents by Inventor Praveen Krishnamurthy
Praveen Krishnamurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11513686Abstract: Accesses between a processor and its external memory is reduced when the processor internally maintains a compressed version of values stored in the external memory. The processor can then refer to the compressed version rather than access the external memory. One compression technique involves maintaining a dictionary on the processor mapping portions of a memory to values. When all of the values of a portion of memory are uniform (e.g., the same), the value is stored in the dictionary for that portion of memory. Thereafter, when the processor needs to access that portion of memory, the value is retrieved from the dictionary rather than from external memory. Techniques are disclosed herein to extend, for example, the capabilities of such dictionary-based compression so that the amount of accesses between the processor and its external memory are further reduced.Type: GrantFiled: May 5, 2020Date of Patent: November 29, 2022Assignee: NVIDIA CorporationInventors: Ram Rangan, Suryakant Patidar, Praveen Krishnamurthy, Wishwesh Anil Gandhi
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Patent number: 11372548Abstract: Some systems compress data utilized by a user mode software without the user mode software being aware of any compression taking place. To maintain that illusion, such systems prevent user mode software from being aware of and/or accessing the underlying compressed states of the data. While such an approach protects proprietary compression techniques used in such systems from being deciphered, such restrictions limit the ability of user mode software to use the underlying compressed forms of the data in new ways. Disclosed herein are various techniques for allowing user-mode software to access the underlying compressed states of data either directly or indirectly. Such techniques can be used, for example, to allow various user-mode software on a single system or on multiple systems to exchange data in the underlying compression format of the system(s) even when the user mode software is unable to decipher the compression format.Type: GrantFiled: May 29, 2020Date of Patent: June 28, 2022Assignee: NVIDIA CorporationInventors: Ram Rangan, Patrick Richard Brown, Wishwesh Anil Gandhi, Steven James Heinrich, Mathias Heyer, Emmett Michael Kilgariff, Praveen Krishnamurthy, Dong Han Ryu
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Patent number: 11263051Abstract: Accesses between a processor and its external memory is reduced when the processor internally maintains a compressed version of values stored in the external memory. The processor can then refer to the compressed version rather than access the external memory. One compression technique involves maintaining a dictionary on the processor mapping portions of a memory to values. When all of the values of a portion of memory are uniform (e.g., the same), the value is stored in the dictionary for that portion of memory. Thereafter, when the processor needs to access that portion of memory, the value is retrieved from the dictionary rather than from external memory. Techniques are disclosed herein to extend, for example, the capabilities of such dictionary-based compression so that the amount of accesses between the processor and its external memory are further reduced.Type: GrantFiled: May 5, 2020Date of Patent: March 1, 2022Assignee: NVIDIA CorporationInventors: Ram Rangan, Suryakant Patidar, Praveen Krishnamurthy, Wishwesh Anil Gandhi
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Publication number: 20210373774Abstract: Some systems compress data utilized by a user mode software without the user mode software being aware of any compression taking place. To maintain that illusion, such systems prevent user mode software from being aware of and/or accessing the underlying compressed states of the data. While such an approach protects proprietary compression techniques used in such systems from being deciphered, such restrictions limit the ability of user mode software to use the underlying compressed forms of the data in new ways. Disclosed herein are various techniques for allowing user-mode software to access the underlying compressed states of data either directly or indirectly. Such techniques can be used, for example, to allow various user-mode software on a single system or on multiple systems to exchange data in the underlying compression format of the system(s) even when the user mode software is unable to decipher the compression format.Type: ApplicationFiled: May 29, 2020Publication date: December 2, 2021Inventors: Ram Rangan, Patrick Richard Brown, Wishwesh Anil Gandhi, Steven James Heinrich, Mathias Heyer, Emmett Michael Kilgariff, Praveen Krishnamurthy, Dong Han Ryu
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Publication number: 20210349639Abstract: Accesses between a processor and its external memory is reduced when the processor internally maintains a compressed version of values stored in the external memory. The processor can then refer to the compressed version rather than access the external memory. One compression technique involves maintaining a dictionary on the processor mapping portions of a memory to values. When all of the values of a portion of memory are uniform (e.g., the same), the value is stored in the dictionary for that portion of memory. Thereafter, when the processor needs to access that portion of memory, the value is retrieved from the dictionary rather than from external memory. Techniques are disclosed herein to extend, for example, the capabilities of such dictionary-based compression so that the amount of accesses between the processor and its external memory are further reduced.Type: ApplicationFiled: May 5, 2020Publication date: November 11, 2021Inventors: Ram Rangan, Suryakant Patidar, Praveen Krishnamurthy, Wishwesh Anil Gandhi
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Publication number: 20210349761Abstract: Accesses between a processor and its external memory is reduced when the processor internally maintains a compressed version of values stored in the external memory. The processor can then refer to the compressed version rather than access the external memory. One compression technique involves maintaining a dictionary on the processor mapping portions of a memory to values. When all of the values of a portion of memory are uniform (e.g., the same), the value is stored in the dictionary for that portion of memory. Thereafter, when the processor needs to access that portion of memory, the value is retrieved from the dictionary rather than from external memory. Techniques are disclosed herein to extend, for example, the capabilities of such dictionary-based compression so that the amount of accesses between the processor and its external memory are further reduced.Type: ApplicationFiled: May 5, 2020Publication date: November 11, 2021Inventors: Ram Rangan, Suryakant Patidar, Praveen Krishnamurthy, Wishwesh Anil Gandhi
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Publication number: 20210304848Abstract: Apparatuses and methods are disclosed for comparing a first biosequence string with a second biosequence string to assess similarity between those biosequence strings. For example, a field programmable gate array (FPGA) can be used to (1) detect substrings of the second biosequence string that are matches to substrings of the first biosequence string, and (2) map the detected substrings of the second biosequence string to corresponding positions in the first biosequence string where the detected substrings are located based on a data structure that links substrings of the first biosequence string to positions in the first biosequence string where the substrings of the first biosequence string are located. These operations can be used to seed an alignment between the first and second biosequence strings that permits comparisons to be performed over longer substrings of the first and second biosequence strings so that similarities between those longer substrings can be quantified.Type: ApplicationFiled: March 23, 2021Publication date: September 30, 2021Inventors: Jeremy Daniel Buhler, Roger Dean Chamberlain, Mark Allen Franklin, Kwame Gyang, Arpith Chacko Jacob, Praveen Krishnamurthy, Joseph Marion Lancaster
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Patent number: 11061571Abstract: In various embodiments, a memory interface unit organizes data within a memory tile to facilitate efficient memory accesses. In an embodiment, a memory tile represents a portion of memory that holds multiple chunks of data, where each chunk is stored either in a non-compressed or in a smaller compressed data format. In an embodiment, the tile is organized to pack multiple compressed chunks together so that multiple compressed chunks can be retrieved from memory with a single read access. In another embodiment, the tile is organized to store redundant copies of compressed chunks so that a compressed chunk can be quickly decompressed within a tile without having to relocate other compressed chunks in the tile. Additional embodiments are further disclosed for allowing efficient accesses to both compressed and non-compressed data.Type: GrantFiled: March 19, 2020Date of Patent: July 13, 2021Assignee: NVIDIA CorporationInventors: Praveen Krishnamurthy, Wishwesh Anil Gandhi
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Patent number: 10957423Abstract: Apparatuses and methods are disclosed for comparing a first biosequence string with a second biosequence string to assess similarity between those biosequence strings. For example, a field programmable gate array (FPGA) can be used to (1) detect substrings of the second biosequence string that are matches to substrings of the first biosequence string, and (2) map the detected substrings of the second biosequence string to corresponding positions in the first biosequence string where the detected substrings are located based on a data structure that links substrings of the first biosequence string to positions in the first biosequence string where the substrings of the first biosequence string are located. These operations can be used to seed an alignment between the first and second biosequence strings that permits comparisons to be performed over longer substrings of the first and second biosequence strings so that similarities between those longer substrings can be quantified.Type: GrantFiled: February 28, 2020Date of Patent: March 23, 2021Assignee: WASHINGTON UNIVERSITYInventors: Jeremy Daniel Buhler, Roger Dean Chamberlain, Mark Allen Franklin, Kwame Gyang, Arpith Chacko Jacob, Praveen Krishnamurthy, Joseph Marion Lancaster
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Publication number: 20200251185Abstract: Apparatuses and methods are disclosed for comparing a first biosequence string with a second biosequence string to assess similarity between those biosequence strings. For example, a field programmable gate array (FPGA) can be used to (1) detect substrings of the second biosequence string that are matches to substrings of the first biosequence string, and (2) map the detected substrings of the second biosequence string to corresponding positions in the first biosequence string where the detected substrings are located based on a data structure that links substrings of the first biosequence string to positions in the first biosequence string where the substrings of the first biosequence string are located. These operations can be used to seed an alignment between the first and second biosequence strings that permits comparisons to be performed over longer substrings of the first and second biosequence strings so that similarities between those longer substrings can be quantified.Type: ApplicationFiled: February 28, 2020Publication date: August 6, 2020Inventors: Jeremy Daniel Buhler, Roger Dean Chamberlain, Mark Allen Franklin, Kwame Gyang, Arpith Chacko Jacob, Praveen Krishnamurthy, Joseph Marion Lancaster
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Patent number: 10580518Abstract: A system and method for performing similarity searching is disclosed wherein programmable logic devices such as field programmable gate arrays (FPGAs) can be used to implement Bloom filters for identifying possible matches between a query and data. The Bloom filters can be implemented in a parallel architecture where the different parallel Bloom filters share access to the same memory units. Further, a hash table may be generated to map a set of strings to keys. In other examples, the hash table may be used to map a set of substrings to a position in a larger string.Type: GrantFiled: January 11, 2017Date of Patent: March 3, 2020Assignee: WASHINGTON UNIVERSITYInventors: Jeremy Daniel Buhler, Roger Dean Chamberlain, Mark Allen Franklin, Kwame Gyang, Arpith Chacko Jacob, Praveen Krishnamurthy, Joseph Marion Lancaster
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Patent number: 10402323Abstract: In one embodiment of the present invention a cache unit organizes data stored in an attached memory to optimize accesses to compressed data. In operation, the cache unit introduces a layer of indirection between a physical address associated with a memory access request and groups of blocks in the attached memory. The layer of indirection—virtual tiles—enables the cache unit to selectively store compressed data that would conventionally be stored in separate physical tiles included in a group of blocks in a single physical tile. Because the cache unit stores compressed data associated with multiple physical tiles in a single physical tile and, more specifically, in adjacent locations within the single physical tile, the cache unit coalesces the compressed data into contiguous blocks. Subsequently, upon performing a read operation, the cache unit may retrieve the compressed data conventionally associated with separate physical tiles in a single read operation.Type: GrantFiled: October 28, 2015Date of Patent: September 3, 2019Assignee: NVIDIA CORPORATIONInventors: Praveen Krishnamurthy, Peter B. Holmquist, Wishwesh Gandhi, Timothy Purcell, Karan Mehra, Lacky Shah
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Patent number: 10338820Abstract: A system architecture conserves memory bandwidth by including compression utility to process data transfers from the cache into external memory. The cache decompresses transfers from external memory and transfers full format data to naive clients that lack decompression capability and directly transfers compressed data to savvy clients that include decompression capability. An improved compression algorithm includes software that computes the difference between the current data word and each of a number of prior data words. Software selects the prior data word with the smallest difference as the nearest match and encodes the bit width of the difference to this data word. Software then encodes the difference between the current stride and the closest previous stride. Software combines the stride, bit width, and difference to yield final encoded data word. Software may encode the stride of one data word as a value relative to the stride of a previous data word.Type: GrantFiled: June 7, 2016Date of Patent: July 2, 2019Assignee: NVIDIA CORPORATIONInventors: Rouslan Dimitrov, Jeff Pool, Praveen Krishnamurthy, Chris Amsinck, Karan Mehra, Scott Cutler
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Patent number: 9934145Abstract: In one embodiment of the present invention a cache unit organizes data stored in an attached memory to optimize accesses to compressed data. In operation, the cache unit introduces a layer of indirection between a physical address associated with a memory access request and groups of blocks in the attached memory. The layer of indirection—virtual tiles—enables the cache unit to selectively store compressed data that would conventionally be stored in separate physical tiles included in a group of blocks in a single physical tile. Because the cache unit stores compressed data associated with multiple physical tiles in a single physical tile and, more specifically, in adjacent locations within the single physical tile, the cache unit coalesces the compressed data into contiguous blocks. Subsequently, upon performing a read operation, the cache unit may retrieve the compressed data conventionally associated with separate physical tiles in a single read operation.Type: GrantFiled: October 28, 2015Date of Patent: April 3, 2018Assignee: NVIDIA CorporationInventors: Praveen Krishnamurthy, Peter B. Holmquist, Wishwesh Gandhi, Timothy Purcell, Karan Mehra, Lacky Shah
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Publication number: 20170351429Abstract: A system architecture conserves memory bandwidth by including compression utility to process data transfers from the cache into external memory. The cache decompresses transfers from external memory and transfers full format data to naive clients that lack decompression capability and directly transfers compressed data to savvy clients that include decompression capability. An improved compression algorithm includes software that computes the difference between the current data word and each of a number of prior data words. Software selects the prior data word with the smallest difference as the nearest match and encodes the bit width of the difference to this data word. Software then encodes the difference between the current stride and the closest previous stride. Software combines the stride, bit width, and difference to yield final encoded data word. Software may encode the stride of one data word as a value relative to the stride of a previous data word.Type: ApplicationFiled: June 7, 2016Publication date: December 7, 2017Inventors: Rouslan DIMITROV, Jeff POOL, Praveen KRISHNAMURTHY, Chris AMSINCK, Karan MEHRA, Scott CUTLER
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Publication number: 20170124255Abstract: A system and method for performing similarity searching is disclosed wherein programmable logic devices such as field programmable gate arrays (FPGAs) can be used to implement Bloom filters for identifying possible matches between a query and data. The Bloom filters can be implemented in a parallel architecture where the different parallel Bloom filters share access to the same memory units. Further, a hash table may be generated to map a set of strings to keys. In other examples, the hash table may be used to map a set of substrings to a position in a larger string.Type: ApplicationFiled: January 11, 2017Publication date: May 4, 2017Inventors: Jeremy Daniel Buhler, Roger Dean Chamberlain, Mark Allen Franklin, Kwame Gyang, Arpith Chacko Jacob, Praveen Krishnamurthy, Joseph Marion Lancaster
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Publication number: 20170123978Abstract: In one embodiment of the present invention a cache unit organizes data stored in an attached memory to optimize accesses to compressed data. In operation, the cache unit introduces a layer of indirection between a physical address associated with a memory access request and groups of blocks in the attached memory. The layer of indirection—virtual tiles—enables the cache unit to selectively store compressed data that would conventionally be stored in separate physical tiles included in a group of blocks in a single physical tile. Because the cache unit stores compressed data associated with multiple physical tiles in a single physical tile and, more specifically, in adjacent locations within the single physical tile, the cache unit coalesces the compressed data into contiguous blocks. Subsequently, upon performing a read operation, the cache unit may retrieve the compressed data conventionally associated with separate physical tiles in a single read operation.Type: ApplicationFiled: October 28, 2015Publication date: May 4, 2017Inventors: Praveen KRISHNAMURTHY, Peter B. HOLMQUIST, Wishwesh GANDHI, Timothy PURCELL, Karan MEHRA, Lacky SHAH
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Publication number: 20170123977Abstract: In one embodiment of the present invention a cache unit organizes data stored in an attached memory to optimize accesses to compressed data. In operation, the cache unit introduces a layer of indirection between a physical address associated with a memory access request and groups of blocks in the attached memory. The layer of indirection—virtual tiles—enables the cache unit to selectively store compressed data that would conventionally be stored in separate physical tiles included in a group of blocks in a single physical tile. Because the cache unit stores compressed data associated with multiple physical tiles in a single physical tile and, more specifically, in adjacent locations within the single physical tile, the cache unit coalesces the compressed data into contiguous blocks. Subsequently, upon performing a read operation, the cache unit may retrieve the compressed data conventionally associated with separate physical tiles in a single read operation.Type: ApplicationFiled: October 28, 2015Publication date: May 4, 2017Inventors: Praveen KRISHNAMURTHY, Peter B. HOLMQUIST, Wishwesh GANDHI, Timothy PURCELL, Karan MEHRA, Lacky SHAH
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Patent number: 9547680Abstract: A system and method for performing similarity searching is disclosed wherein programmable logic devices such as field programmable gate arrays (FPGAs) can be used to implement Bloom filters for identifying possible matches between a query and data. The Bloom filters can be implemented in a parallel architecture where the different parallel Bloom filters share access to the same memory units.Type: GrantFiled: August 19, 2013Date of Patent: January 17, 2017Assignee: Washington UniversityInventors: Jeremy Daniel Buhler, Roger Dean Chamberlain, Mark Allen Franklin, Kwame Gyang, Arpith Chacko Jacob, Praveen Krishnamurthy, Joseph Marion Lancaster
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Patent number: 9287875Abstract: Circuits and methods for controlling electrical coupling by a load switch are disclosed. In an embodiment, the load switch includes a pass element, level-shift circuit and low-resistance active path. The pass element is configured to be coupled to a power supply and a load, and is configured to electrically couple the power supply with the load during ON-state and electrically decouple the power supply from the load during OFF-state. The level-shift circuit includes a first transistor and pull-up resistor and is configured to generate a level-shifted signal in response to an enable signal, and enable the ON-state and the OFF-state of the pass element based on first and second voltages of the level-shifted signal. The low-resistance active path is coupled in parallel with the pull-up resistor for shunting the pull-up resistor in the OFF-state by providing a path for a leakage current of the first transistor in the OFF-state.Type: GrantFiled: May 7, 2014Date of Patent: March 15, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Alok Kumar, Fenish Padinjaroot Prakasan, Rajkumar Jayaraman, Kalyan Cherukuri, Praveen Krishnamurthy