Abstract: In a design verification apparatus, a priority resolver selects one or more verification datasets for verifying a procedure described in a design specification of a target product, in response to a verification request for that procedure. The priority resolver determines a priority score of each parameter that the selected verification datasets specify as a constraint on the procedure. A verification order resolver determines a verification order of the selected verification datasets, based on the priority scores determined by the priority resolver. An output processor produces data identifying the verification datasets, together with indication of the determined verification order.

Abstract: A design verification apparatus includes a processor to produce and place constraint conditions on verification datasets provided to verify a first design specification of a target product. The processor produces those constraint conditions from a second design specification of the target product, based on links from units of processing which constitute a procedure defined for each verification item in the second design specification to units of processing in the first design specification. The processor outputs data identifying the resulting verification datasets having the constraint conditions, together with their corresponding verification items.

Abstract: In a design verification apparatus, a priority resolver selects one or more verification datasets for verifying a procedure described in a design specification of a target product, in response to a verification request for that procedure. The priority resolver determines a priority score of each parameter that the selected verification datasets specify as a constraint on the procedure. A verification order resolver determines a verification order of the selected verification datasets, based on the priority scores determined by the priority resolver. An output processor produces data identifying the verification datasets, together with indication of the determined verification order.

Abstract: A design verification apparatus includes a dataset generator to generate verification datasets which associate each unit process of a plurality of procedures (processing scenarios) described in a design specification of a target product with an identifier (label) designating which portion of the design specification is to be verified. A process priority setting unit assigns a process priority to each verification dataset according to specified identifiers. An output processor outputs data identifying the verification datasets, together with explicit indication of their process priorities.

Abstract: In accordance with a particular embodiment of the present invention, a method is offered that includes generating an automatic test case generation using model checking for web applications, the automatic test case generation including: developing a specification; verifying a property using model checking on the specification; obtaining a counterexample, whereby the counterexample is mapped to a web test case; and executing the web test case on an implementation. In more specific embodiments, the method includes generating counterexamples by negating a desirable property and then model checking the specification, whereby the counterexamples represent a set of witnesses that are mapped to the web test case; and executing the web test case on the implementation. In still other specific embodiments, the generating step and the executing step are repeated on available properties and on their available counterexamples. The witnesses can be mapped to the web test case through selected framework technology.

Abstract: A method for high level validation of a design includes receiving input associated with a design; generating a message diagram in response to the input, wherein the message diagram describes a relationship of messages communicated between multiple processes; resolving at least one scenario from the message diagram, wherein the scenario comprises a particular sequence of messages identified by the message diagram; generating a state machine operable to receive and transmit at least some of the messages identified by the message diagram according to the scenario; and testing an implementation of the design using the state machine.