Abstract: Capacitive digital-to-analog converters (DACs) with shaped output current are disclosed. In certain embodiments, a capacitive DAC converter cell for a capacitive DAC includes a capacitor connected between an output terminal and an internal node, a first current source, a first switch connected in series with the first current source between the internal node and a first voltage, a second current source, a second switch connected in series with the second current source between the internal node and a second voltage, a third switch connected between the internal node and the first voltage, and a fourth switch connected between the internal node and the second voltage.

Abstract: This disclosure relates generally to a system for mitigating error in an amplifier. The system may include a loop filter; a driver; a digital-to-analog converter (DAC) configured to source and to sink current; an edge selector configured to determine a first delay between the driver receiving a signal to provide a driver output signal and the driver providing the driver output signal; a timing circuit configured to determine a second delay between the DAC receiving a signal to provide a DAC output current and the DAC providing the DAC output current; and at least one controller configured to control the DAC to source or to sink the DAC output current at a time corresponding to a beginning of the driver output signal, and control the DAC to stop sourcing or sinking the DAC output current at a time corresponding to an end of the driver output signal.

Abstract: In some embodiments, an analog-to-digital converter (ADC) architecture can be implemented to process a signal from a charge output sensor. The ADC architecture can include a summing node for receiving a sensor signal from the charge output sensor, and an output node implemented to provide a digital signal representative of the sensor signal. The ADC architecture can further include a charge amplifier implemented to receive an analog signal from the summing node as an input analog signal and generate an output analog signal with a gain, and an ADC circuit implemented to generate the digital signal based on the output analog signal from the charge amplifier. The ADC architecture can further include a feedback circuit implemented between the output node and the summing node.

Abstract: In some embodiments, an audio amplifier can include an input for receiving a signal to be amplified, and an amplification stage configured to amplify the signal based on pulse width modulation and provide the amplified signal at an output node. The audio amplifier can further include a feedback circuit implemented between the output node and the input node. The feedback circuit can include a series arrangement of a high bandwidth input common mode loop and a low bandwidth output common mode loop, with the low bandwidth output common mode loop configured to provide a desired phase change for the high bandwidth input common mode loop.