Abstract: In some embodiments, an analog-to-digital converter (ADC) architecture can be implemented to process a signal from a charge output sensor. The ADC architecture can include a summing node for receiving a sensor signal from the charge output sensor, and an output node implemented to provide a digital signal representative of the sensor signal. The ADC architecture can further include a charge amplifier implemented to receive an analog signal from the summing node as an input analog signal and generate an output analog signal with a gain, and an ADC circuit implemented to generate the digital signal based on the output analog signal from the charge amplifier. The ADC architecture can further include a feedback circuit implemented between the output node and the summing node.

Abstract: In some embodiments, an audio amplifier can include an input for receiving a signal to be amplified, and an amplification stage configured to amplify the signal based on pulse width modulation and provide the amplified signal at an output node. The audio amplifier can further include a feedback circuit implemented between the output node and the input node. The feedback circuit can include a series arrangement of a high bandwidth input common mode loop and a low bandwidth output common mode loop, with the low bandwidth output common mode loop configured to provide a desired phase change for the high bandwidth input common mode loop.