Patents by Inventor Praveen Mosalikanti
Praveen Mosalikanti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085973Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Praveen MOSALIKANTI, Nasser A. KURD, Alexander GENDLER
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Publication number: 20240077924Abstract: Embodiments of a power regulation circuit that ameliorates a first and second droop in a power source voltage that powers a processing core are disclosed. The power regulation circuit includes a first droop detector, a second droop detector and a frequency slowdown detection circuit. The first droop detector generates a first droop detection signal in a first detection state in response to detecting a first droop in the power source voltage. The second droop detector generates a second droop detection signal in a second detection state in response to detecting a second droop in the power source voltage. The frequency slowdown detection circuit to generate a frequency slowdown signal in a slowdown state in response to at least one of the first droop detection signal being in the first detection state and the second droop detection signal being in the second detection state.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Inventors: Praveen Mosalikanti, Robert Mongrain, Xingjian Cai, Yihong Yang, Long Wang
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Patent number: 11847011Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.Type: GrantFiled: February 22, 2021Date of Patent: December 19, 2023Assignee: Intel CorporationInventors: Praveen Mosalikanti, Nasser A. Kurd, Alexander Gendler
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Publication number: 20230314488Abstract: A single droop detector and an asynchronous frequency recovery circuit may be used to slow down a frequency asynchronously when a voltage droop is detected and exit the droop event synchronously by gradually changing an electronic oscillator buffer capacitance until the frequency has been fully restored. This combination of a single droop detector and an asynchronous frequency recovery circuit may provide reduced detection and response latency. This solution may also provide improved performance in the presence of multiple voltage droop events that occur before a frequency has been fully restored from the previous droop. This solution also reduces or eliminates frequency overshoots and secondary voltage droops.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Praveen Mosalikanti, Vaughn J. Grossnickle, Nasser A. Kurd
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Patent number: 11461504Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.Type: GrantFiled: November 2, 2020Date of Patent: October 4, 2022Assignee: Intel CorporationInventors: Nasser Kurd, Praveen Mosalikanti, Thripthi Hegde, Mark Neidengard, Vaughn Grossnickle, Qi S. Wang, Kandadai Ramesh
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Patent number: 11211934Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.Type: GrantFiled: September 22, 2020Date of Patent: December 28, 2021Assignee: Intel CorporationInventors: Praveen Mosalikanti, Qi Wang, Mark L. Neidengard, Vaughn J. Grossnickle, Nasser A. Kurd
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Patent number: 11188117Abstract: An apparatus is provided for low latency adaptive clocking, the apparatus comprises: a first power supply rail to provide a first power; a second power supply rail to provide a second power; a third power supply rail to provide a third power; a voltage divider coupled to the first, second, and third power supply rails; a bias generator coupled to voltage divider and the third power supply rail; an oscillator coupled to the bias generator and the first supply rail; and a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.Type: GrantFiled: September 6, 2018Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Praveen Mosalikanti, Nasser Kurd
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Patent number: 11048284Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.Type: GrantFiled: September 10, 2019Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Praveen Mosalikanti, Gerhard Schrom, Vaughn J. Grossnickle, Nasser A. Kurd
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Publication number: 20210181831Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.Type: ApplicationFiled: February 22, 2021Publication date: June 17, 2021Applicant: Intel CorporationInventors: Praveen MOSALIKANTI, Nasser A. KURD, Alexander GENDLER
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Publication number: 20210083678Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.Type: ApplicationFiled: September 22, 2020Publication date: March 18, 2021Applicant: Intel CorporationInventors: Praveen Mosalikanti, Qi Wang, Mark L. Neidengard, Vaughn J. Grossnickle, Nasser A. Kurd
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Patent number: 10928886Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.Type: GrantFiled: February 25, 2019Date of Patent: February 23, 2021Assignee: Intel CorporationInventors: Praveen Mosalikanti, Nasser A. Kurd, Alexander Gendler
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Publication number: 20210049307Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.Type: ApplicationFiled: November 2, 2020Publication date: February 18, 2021Applicant: Intel CorporationInventors: Nasser Kurd, Praveen Mosalikanti, Thripthi Hegde, Mark Neidengard, Vaughn Grossnickle, Qi S. Wang, Kandadai Ramesh
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Patent number: 10824764Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.Type: GrantFiled: June 27, 2018Date of Patent: November 3, 2020Assignee: Intel CorporationInventors: Nasser Kurd, Praveen Mosalikanti, Thripthi Hegde, Mark Neidengard, Vaughn Grossnickle, Qi S. Wang, Kandadai Ramesh
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Patent number: 10790838Abstract: Dynamic voltage frequency scaling to transition to a target clock frequency and associated target voltage is provided. Dynamic voltage frequency scaling to a different clock frequency is performed by gradually changing the clock frequency using discrete variable-size steps, while dynamically switching to faster or slower reference clock frequencies as appropriate to harmonize the frequency trajectory with system requirements.Type: GrantFiled: May 14, 2019Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Praveen Mosalikanti, Vaughn J. Grossnickle, Syed Feruz Syed Farooq, Mark Neidengard, Nasser A. Kurd
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Patent number: 10790832Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.Type: GrantFiled: March 22, 2018Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Praveen Mosalikanti, Qi Wang, Mark L. Neidengard, Vaughn J. Grossnickle, Nasser A. Kurd
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Publication number: 20200272197Abstract: An apparatus is provided for low latency adaptive clocking, the apparatus comprises: a first power supply rail to provide a first power; a second power supply rail to provide a second power; a third power supply rail to provide a third power; a voltage divider coupled to the first, second, and third power supply rails; a bias generator coupled to voltage divider and the third power supply rail; an oscillator coupled to the bias generator and the first supply rail; and a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.Type: ApplicationFiled: September 6, 2018Publication date: August 27, 2020Applicant: Intel CorporationInventors: Praveen Mosalikanti, Nasser Kurd
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Publication number: 20200272220Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.Type: ApplicationFiled: February 25, 2019Publication date: August 27, 2020Inventors: Praveen MOSALIKANTI, Nasser KURD, Alexander GENDLER
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Patent number: 10707877Abstract: Switched adaptive clocking is provided. A switched adaptive clocking circuit includes a digitally controlled oscillator, a clock generator and a glitch-free multiplexer. The switched adaptive clocking circuit to adaptively switch a source of an output clock from a main clock generated by a clock source to a digitally controlled oscillator clock generated by a digitally controlled oscillator upon detection of a voltage droop, and to quickly switch back to the main clock after recovery from the voltage droop.Type: GrantFiled: June 27, 2019Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Turbo Majumder, Minki Cho, Carlos Tokunaga, Praveen Mosalikanti, Nasser A. Kurd, Muhammad M. Khellah
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Patent number: 10614774Abstract: Techniques and mechanisms for an integrated circuit (IC) chip to generate a clock signal for use by one or more resources of the IC chip. In an embodiment, a clock signal is generated with phase-locked loop (PLL) circuitry of an IC chip based on a cyclical signal which is provided to the IC chip by an external source. A supply voltage provided to the PLL circuitry is automatically updated based on one of a requested frequency for the clock signal, a frequency of the received cyclical signal, or a voltage of a control signal used by a voltage controlled oscillator of the PLL circuitry. In another embodiment, a series of incremental changes to a frequency of the clock signal is automatically performed according to a predefined overclocking scheme or underclocking scheme.Type: GrantFiled: June 27, 2018Date of Patent: April 7, 2020Assignee: Intel CorporationInventors: Nasser Kurd, Daniel Ragland, Ameya Ambardekar, John Fallin, Praveen Mosalikanti, Vaughn J. Grossnickle
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Publication number: 20200005728Abstract: Techniques and mechanisms for an integrated circuit (IC) chip to generate a clock signal for use by one or more resources of the IC chip. In an embodiment, a clock signal is generated with phase-locked loop (PLL) circuitry of an IC chip based on a cyclical signal which is provided to the IC chip by an external source. A supply voltage provided to the PLL circuitry is automatically updated based on one of a requested frequency for the clock signal, a frequency of the received cyclical signal, or a voltage of a control signal used by a voltage controlled oscillator of the PLL circuitry. In another embodiment, a series of incremental changes to a frequency of the clock signal is automatically performed according to a predefined overclocking scheme or underclocking scheme.Type: ApplicationFiled: June 27, 2018Publication date: January 2, 2020Applicant: Intel CorporationInventors: Nasser Kurd, Daniel Ragland, Ameya Ambardekar, John Fallin, Praveen Mosalikanti, Vaughn J. Grossnickle