Patents by Inventor Praveen Nalla

Praveen Nalla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100136788
    Abstract: Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.
    Type: Application
    Filed: February 3, 2010
    Publication date: June 3, 2010
    Applicant: Lam Research Corporation
    Inventors: Zhonghui Alex Wang, Tiruchirapalli Arunagiri, Fritz C. Redeker, Yezdi Dordi, John Boyd, Mikhail Korolik, Arthur M. Howald, William Thie, Praveen Nalla
  • Patent number: 7709400
    Abstract: Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: May 4, 2010
    Assignee: Lam Research Corporation
    Inventors: Zhonghui Alex Wang, Tiruchirapalli Arunagirí, Fritz C. Redeker, Yezdi Dordi, John Boyd, Mikhail Korolik, Arthur M. Howald, William Thie, Praveen Nalla
  • Publication number: 20090304914
    Abstract: The embodiments fill the need enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect with good electro-migration performance and with reduced risk of stress-induce voiding of copper interconnect. Electromigration and stress-induced voiding are affected by the adhesion between the barrier layer and the copper layer. A functionalization layer is deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect. The functionalization layer forms strong bonds with barrier layer and with copper to improve adhesion property between the two layers. An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in order to improve electromigration performance of the copper interconnect is provided.
    Type: Application
    Filed: December 13, 2006
    Publication date: December 10, 2009
    Applicant: Lam Research Corporation
    Inventors: Praveen Nalla, William Thie, John Boyd, Tiruchirapalli Arunagiri, Hyungsuk Alexander Yoon, Fritz C. Redeker, Yezdi Dordi
  • Publication number: 20080280456
    Abstract: Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.
    Type: Application
    Filed: May 8, 2007
    Publication date: November 13, 2008
    Inventors: Zhonghui Alex Wang, Tiruchirapalli Arunagiri, Fritz C. Redeker, Yezdi Dordi, John Boyd, Mikhail Korolik, Arthur M. Howald, William Thie, Praveen Nalla
  • Publication number: 20080152823
    Abstract: A self-limiting electroless plating process is provided to plate thin films with improved uniformity. The process comprises dispensing an electroless plating solution onto a substrate to form a quiescent solution layer from which a conformal plated layer plates onto a surface of the substrate by a redox reaction. The redox reaction occurs at the surface of the substrate between a reducing agent ion and a plating ion and produces an oxidized ion. Because the solution is quiescent, a boundary layer forms within the solution layer adjacent to the surface. The boundary layer is characterized by a concentration gradient of the oxidized ion. Diffusion of the reducing agent ion through the boundary layer controls the redox reaction. The quiescent solution layer can be maintained until the reducing agent ion in the solution layer is substantially depleted.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 26, 2008
    Inventors: John Boyd, Yezdi Dordi, Tiruchirapalli Arunagiri, William Thie, Fritz C. Redeker, Praveen Nalla